82443BX Datasheet, PDF (25/132 Pages) Intel Corporation – Host Bridge/Controller

Signal Description
Table 2-10. Strapping Options
Signal
Register
Name[bit]
Description
MAB13#
MAB12#
MAB11#
MAB10
MAB9#
MAB8#
MAB7#
MAB6#
A[15]#
A7#
NBXCFG[13]
NBXCFG[2]
PMCR[3]
PMCR[1]
DRAMC[5]
none
none
none
Reserved.
Host Frequency Select: If MAB#12 is strapped to 0, the host bus frequency is 60/
66 MHz. If MAB#12 is strapped to 1, the host bus frequency is 100 MHz. An
internal pull-down is used to provide the default setting of 66 MHz.
In-Order Queue Depth Enable. If MAB11# is strapped to 0 during the rising edge
of PCIRST#, then the 82442BX will drive A7# low during the CPURST#
deassertion. This forces the CPU bus to be configured for non-pipelined operation.
If MAB11 is strapped to 1 (default), then the 82443BX does not drive the A7# low
during reset, and A7# is sampled in default non-driven state (i.e. pulled-up as far as
GTL+ termination is concerned) then the maximum allowable queue depth by the
CPU bus protocol is selected (i.e., 8).
Note that internal pull-up is used to provide pipelined bus mode as a default.
Quick Start Select. The value on this pin at reset determines which stop clock
mode is used.
MAB10 = 0 (default) for normal stop clock mode. If MAB10 = 1 during the rising
edge of PCIRST#, then the 82443BX will drive A15# low during CPURST#
deassertion. This will configure the CPU for Quick Start mode of operation.
Note that internal pull-down is used to provide normal stop clock mode as a default.
AGP Disable: When strapped to a 1, the AGP interface is disabled, all AGP signals
are tri-stated and isolated. When strapped to a 0 (default), the AGP interface is
enabled.
When MMCONFIG is strapped active, we require that AGP_DISABLE is also
strapped active. When MMCONFIG is strapped inactive, AGP_DISABLE can be
strapped active or inactive but IDSEL_REDIRECT (bit 16 in NBXCFG register)
must never be activated.
This signal has an internal pull-down resistor.
Reserved.
Memory Module Configuration, MMCONFIG: When strapped to a 1, the
82443BX configures its DRAM interface in a 430-TX compatible manner. These
unused inputs are isolated while unused outputs are tri-stated: RASB[5:0]#/
CSB[5:0]#, CKE[3:2]/CSA[7:6]#, CKE[5:4]/CSB[7:6]#, CASB[5,1]#/DQMB[5,1],
GCKE/CKE1, MAA[13:0], DCLKO.
When strapped to a 0 (default), the 82443BX DRAM signal are used normally.
IDSEL_REDIRECT (bit 16 in NBXCFG register) is programmed by BIOS, before it
begins with device enumeration process. The combination of SDRAMPWR
(SDRAMC register) and MMCONFIG (DRAMC register) determine the functioning
of the CKE signals. Refer to the DRAMC register for more details.
Note that internal pull-down is used to set the DRAM interface to a normal
configuration, as a default.
Host Bus Buffer Mode Select: When strapped 0, the desktop GTL+ 66 MHz or
100 MHz host bus buffers are used (default).
When strapped ‘1’, the mobile Low Power GTL+ 66 MHz host bus buffers are
selected.
Note that internal pull-down is used to set the host bus buffers to a desktop
configuration as a default. External pull-up therefore is needed for mobile systems,
only.
Quick Start Select. The value on A15# sampled at the rising edge of CPURST#
will reflect if the quick start/stop clock mode is enabled in the processors.
In-order Queue Depth Status. The value on A[7]# sampled at the rising edge of
CPURST# reflects if the IOQD is set to 1 or maximum allowable by the CPU bus.
NOTE:
1. Proper strapping must be used to define logical values for these signals. Default value “0”, or “1” provided by
the internal pull-up or pull-down resistor can be overridden by the external pull-up, or pull-down resistor.
82443BX Host Bridge Datasheet
2-11