82443BX Datasheet, PDF (76/132 Pages) Intel Corporation – Host Bridge/Controller

Register Description
3.4.3
PCICMD1—PCI-to-PCI Command Register (Device 1)
Address Offset:
Default:
Access:
Size
04–05h
0000h
Read/Write
16 bits
Bit
15:10
9
8
7
6
5
4
3
2
1
0
Descriptions
Reserved.
Fast Back-to-Back: Not Applicable. Hardwired to 0.
SERR# Enable (SERRE1). When enabled the SERR# signal driver (common for PCI and AGP)
is enabled for error conditions that occur on AGP.If both SERRE and SERRE1 are reset to 0,
then SERR# is never driven by the 82443BX. Also, if this bit is set and the Parity Error Response
Enable Bit (Dev 01h, Register 3Eh, Bit 0) is set, then the 82443BX will report ADDRESS and
DATA parity errors on AGP.
1 = Enable.
0 = Disable.
Address/Data Stepping. Not applicable. Hardwired to 0.
Parity Error Enable (PERRE1). Hardwired to 0.
Reserved.
Memory Write and Invalidate Enable: Not applicable. However, supported as a read/write bit
to avoid the problems with normal PCI-to-PCI Bridge configuration software.
Special Cycle Enable: Not applicable. However, supported as a read/write bit to avoid the
problems with normal PCI-to-PCI Bridge configuration software.
Bus Master Enable (BME1): Not applicable. However, supported as a read/write bit to avoid
the problems with normal PCI-to-PCI Bridge configuration software.
Memory Access Enable (MAE1): Not applicable. However, supported as a read/write bit to
avoid the problems with normal PCI-to-PCI Bridge configuration software.
I/O Access Enable (IOAE1): Not applicable. However, supported as a read/write bit to avoid
the problems with normal PCI-to-PCI Bridge configuration software.
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82443BX Host Bridge Datasheet