82443BX Datasheet, PDF (106/132 Pages) Intel Corporation – Host Bridge/Controller

Functional Description
DRAM Register Programming
The Serial Presence Detect ports are used to determine Refresh Rate, MA and MD Buffer Strength,
Row Type (on a row by row basis), EDO Timings, SDRAM Timings, Row Sizes and Row Page
Sizes. Table 4-9 lists a subset of the data available through the on board Serial Presence Detect
ROM on each DIMM.
Table 4-9. Data Bytes on DIMM Used for Programming DRAM Registers
Byte
2
3
4
5
11
12
17
36-41
42
Function
Memory Type (EDO, SDRAM)
# of Row Addresses, not counting Bank Addresses
# of Column Addresses
# of banks of DRAM (Single or Double sided) DIMM
ECC, no ECC
Refresh Rate
# Banks on each SDRAM Device
Access Time from Clock for CAS# Latency 1 through 7
Data Width of SDRAM Components
Table 4-9 is only a subset of the defined SPD bytes on the DIMMs. For example, to program the
DRB (DRAM Row Boundary) registers, the size of each row must be determined. The number of
row addresses (byte 3) plus the number of column addresses (byte 4) plus the number of banks on
each SDRAM device (byte 17) collectively determines the total address depth of a particular row of
SDRAM. Since a row is always 64 data bits wide, the size of the row is easily determined for
programming the DRB registers.
The 82443BX uses the DRAM Row Type information in conjunction with the DRAM timings set
in the DRAM Timing Register to configure DRAM accesses optimally.
4.3.2
DRAM Address Translation and Decoding
The 82443BX supports 16 and 64 Mbit DRAM devices. The 82443BX supports a 2 KB, 4 KB and
8 KB page sizes (for SDRAM only). Page size varies per row depending on how many column
address lines are used for a given row. Rows containing SDRAMs with 8 column lines have a 2 KB
page size. Those with 9 column lines have a 4 KB page size and those with 10 column address lines
have an 8 KB page size. In systems with EDO memory, a fixed 2 KB page size is used. The
multiplexed row/column address to the DRAM memory array is provided by the MA[13:0] signals.
Row and Column address multiplexing on the MA[13:0] lines is determined on a row by row basis
allowing for three possible page sizes. SDRAMs have either 8, 9 or 10 column lines allowing for
2 KB, 4 KB or 8 KB page sizes. The 82443BX supports only a 2 KB page size with EDO DRAMs.
The page size is determined primarily by the row size and type (SDRAM).
When EDO DRAM is used, the 82443BX will open at most one page at a time. That is, one RAS#
line will be asserted at any time. When SDRAM is used, either 2 or 4 pages can be open at any time
within any row. If a row contains SDRAMs based on 16Mb technology (i.e., 12x8/9/10 devices)
then two pages can be open at a time within that row. If a row contains SDRAMs based on 64Mb
technology, (i.e., 14x8/9/10 devices) then four pages can be open at a time within that row.
4-20
82443BX Host Bridge Datasheet