AC82GL40-SLB95 Datasheet, PDF (80/98 Pages) Intel Corporation – Intel® Celeron® Mobile Processor Dual-Core on 45-nm Process

Package Mechanical Specifications and Pin Information
Table 22. Signal Description (Sheet 6 of 7)
Name
Type
Description
RESET#
RS[2:0]#
RSVD
SLP#
SMI#
STPCLK#
TCK
TDI
TDO
TEST1, TEST2,
TEST3,
TEST4,
TEST5,
TEST6
THRMDA
THRMDC
Input
Asserting the RESET# signal resets the processor to a known state and invalidates
its internal caches without writing back any of their contents. For a power-on
Reset, RESET# must stay active for at least two milliseconds after V_CC and BCLK
have reached their proper specifications. On observing active RESET#, both FSB
agents deasserts their outputs within two clocks. All processor straps must be valid
within the specified setup time before RESET# is deasserted. There is a 55-Ω
(nominal) on die pull-up resistor on this signal.
Input
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect the
appropriate pins of both FSB agents.
Reserved These pins are RESERVED and must be left unconnected on the board. However, it
/No is recommended that routing channels to these pins on the board be kept open for
Connect possible future use.
Input
SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter
the Sleep state. During Sleep state, the processor stops providing internal clock
signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state does not recognize snoops or interrupts. The processor
recognizes only assertion of the RESET# signal, deassertion of SLP#, and removal
of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits
Sleep state and returns to Stop-Grant state, restarting its internal clock signals to
the bus and processor core units. If DPSLP# is asserted while in the Sleep state,
the processor exits the Sleep state and transition to the Deep Sleep state.
Input
SMI# (System Management Interrupt) is asserted asynchronously by system logic.
On accepting a System Management Interrupt, the processor saves the current
state and enters System Management Mode (SMM). An SMI Acknowledge
transaction is issued and the processor begins program execution from the SMM
handler.
If an SMI# is asserted during the deassertion of RESET#, then the processor
tristates its outputs.
Input
STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power
Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and
stops providing internal clock signals to all processor core units except the FSB and
APIC units. The processor continues to snoop bus transactions and service
interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor
restarts its internal clock to all units and resumes execution. The assertion of
STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.
Input
TCK (Test Clock) provides the clock input for the processor Test Bus (also known as
the Test Access Port).
Input
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
Output
TDO (Test Data Out) transfers serial test data out of the processor. TDO provides
the serial output needed for JTAG specification support.
Input
TEST1 and TEST2 must have a stuffing option of separate pulldown resistors to
V_SS. For the purpose of testability, route the TEST3 and TEST5 signals through a
ground-referenced Zo=55 Ω trace that ends in a via that is near a GND via and is
accessible through an oscilloscope connection.
Other
Other
Thermal Diode Anode.
Thermal Diode Cathode.
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