AC82GL40-SLB95 Datasheet, PDF (12/98 Pages) Intel Corporation – Intel® Celeron® Mobile Processor Dual-Core on 45-nm Process

Low Power Features
Figure 2. Core Low-Power States
Stop
Grant
C1/MWAIT
STPCLK#
asserted
STPCLK#
deasserted
STPCLK#
STPCLK#
deasserted
STPCLK# ^asserted
deasserted
STPCLK#
asserted
Core state
break
HLT instruction
C1/Auto
Halt
MWAIT(C1)
Halt break
C0
P_LVL2 or
MWAIT(C2)
Core State
break
Core state
break
C2^†
P_LVL4
P_LVL3 or
MWAIT(C4)
Core MWAIT(C3)
C4^{† ‡}
state
break
C3^†
break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
e state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)
STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4.
Core C4 state supports the package level Deep C4 sub-state.
2.1.1
2.1.1.1
2.1.1.2
Core Low-Power States
C0 State
This is the normal operating state of the processor.
C1/AutoHALT Powerdown State
C1/AutoHALT is a low-power state entered when the processor core executes the HALT
instruction. The processor core transitions to the C0 state upon the occurrence of
SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# causes the
processor to immediately initialize itself.
A System Management Interrupt (SMI) A System Management Interrupt (SMI) handler
returns execution to either Normal state or the C1/AutoHALT Powerdown state. See the
Intel® 64 and IA-32 Intel® Architecture Software Developer's Manual, Volume 3A/3B:
System Programmer's Guide for more information.
The system can generate a STPCLK# while the processor is in the C1/AutoHALT
Powerdown state. When the system deasserts the STPCLK# interrupt, the processor
returns execution to the HALT state.
The processor in C1/AutoHALT powerdown state process only the bus snoops. The
processor enters a snoopable sub-state (not shown in Figure 2) to process the snoop
and then return to the C1/AutoHALT Powerdown state.
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Datasheet