AC82GL40-SLB95 Datasheet, PDF (16/98 Pages) Intel Corporation – Intel® Celeron® Mobile Processor Dual-Core on 45-nm Process

Low Power Features
Caution:
2.3
• The processor controls voltage ramp rates internally to ensure glitch-free
transitions.
• Low transition latency and large number of transitions possible per second:
— Processor core (including L2 cache) is unavailable for up to 10 μs during the
frequency transition.
— The bus protocol (BNR# mechanism) is used to block snooping.
• Improved Intel® Thermal Monitor mode:
— When the on-die thermal sensor indicates that the die temperature is too high
the processor can automatically perform a transition to a lower frequency and
voltage specified in a software-programmable MSR.
— The processor waits for a fixed time period. If the die temperature is down to
acceptable levels, an up-transition to the previous frequency and voltage point
occurs.
— An interrupt is generated for the up and down Intel Thermal Monitor transitions
enabling better system-level thermal management.
• Enhanced thermal management features:
— Digital Thermal Sensor and Out of Specification detection.
— Intel Thermal Monitor 1 (TM1) in addition to Intel Thermal Monitor 2 (TM2) in
case of unsuccessful TM2 transition.
— Dual core thermal management synchronization.
Each core in the dual-core processor implements an independent MSR for controlling
Enhanced Intel SpeedStep Technology, but both cores must operate at the same
frequency and voltage. The processor has performance state coordination logic to
resolve frequency and voltage requests from the two cores into a single frequency and
voltage request for the package as a whole. If both cores request the same frequency
and voltage, then the processor will transition to the requested common frequency and
voltage. If the two cores have different frequency and voltage requests, then the
processor will take the highest of the two frequencies and voltages as the resolved
request and transition to that frequency and voltage.
Enhanced Intel SpeedStep Technology transitions are multistep processes
that require clocked control. These transitions cannot occur when the processor is in
the Sleep or Deep Sleep package low-power states since processor clocks are not
active in these states.
Low-Power FSB Features
The processor incorporates FSB low-power enhancements:
• Dynamic On Die Termination disabling
• Low V_CCP (I/O termination voltage)
The On Die Termination on the processor FSB buffers is disabled when the signals are
driven low, resulting in power savings. The low I/O termination voltage is on a
dedicated voltage plane independent of the core voltage, enabling low I/O switching
power at all times.
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Datasheet