AC82GL40-SLB95 Datasheet, PDF (75/98 Pages) Intel Corporation – Intel® Celeron® Mobile Processor Dual-Core on 45-nm Process

Package Mechanical Specifications and Pin Information
4.3
Alphabetical Signals Reference
Table 22.
Name
A[35:3]#
A20M#
ADS#
Signal Description (Sheet 1 of 7)
Type
Input/
Output
Input
Input/
Output
Description
A[35:3]# (Address) define a 2³⁶-byte physical memory address space. In sub-
phase 1 of the address phase, these pins transmit the address of a transaction. In
sub-phase 2, these pins transmit transaction type information. These signals must
connect the appropriate pins of both agents on the processor FSB. A[35:3]# are
source synchronous signals and are latched into the receiving buffers by
ADSTB[1:0]#. Address signals are used as straps which are sampled before
RESET# is deasserted.
If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit
20 (A20#) before looking up a line in any internal cache and before driving a read/
write transaction on the bus. Asserting A20M# emulates the 8086 processor's
address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only
supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an Input/Output write instruction, it must be valid along with the TRDY#
assertion of the corresponding Input/Output Write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the transaction
address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new transaction.
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and
falling edges. Strobes are associated with signals as shown below.
ADSTB[1:0]#
Input/
Output
Signals
Associated Strobe
REQ[4:0]#, A[16:3]# ADSTB[0]#
A[35:17]#
ADSTB[1]#
BCLK[1:0]
BNR#
BPM[2:1]#
BPM[3,0]#
BPRI#
BR0#
Input
Input/
Output
Output
Input/
Output
Input
Input/
Output
The differential pair BCLK (Bus Clock) determines the FSB frequency. All FSB
agents must receive these signals to drive their outputs and latch their inputs.
All external timing parameters are specified with respect to the rising edge of
BCLK0 crossing V_CROSS.
BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is
unable to accept new bus transactions. During a bus stall, the current bus owner
cannot issue any new transactions.
BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals.
They are outputs from the processor which indicate the status of breakpoints and
programmable counters used for monitoring processor performance. BPM[3:0]#
should connect the appropriate pins of all processor FSB agents.This includes
debug or performance monitoring tools.
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the FSB. It must
connect the appropriate pins of both FSB agents. Observing BPRI# active (as
asserted by the priority agent) causes the other agent to stop issuing new
requests, unless such requests are part of an ongoing locked operation. The
priority agent keeps BPRI# asserted until all of its requests are completed, then
releases the bus by deasserting BPRI#.
BR0# is used by the processor to request the bus. The arbitration is done between
processor (Symmetric Agent) and (G)MCH (High Priority Agent).
Datasheet
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