AC82GL40-SLB95 Datasheet, PDF (22/98 Pages) Intel Corporation – Intel® Celeron® Mobile Processor Dual-Core on 45-nm Process

Electrical Specifications
Table 2.
3.4
3.5
Voltage Identification Definition (Sheet 4 of 4)
VID6
1
1
1
1
1
1
1
1
1
1
1
1
VID5
1
1
1
1
1
1
1
1
1
1
1
1
VID4
1
1
1
1
1
1
1
1
1
1
1
1
VID3
0
0
0
0
1
1
1
1
1
1
1
1
VID2
1
1
1
1
0
0
0
0
1
1
1
1
VID1
0
0
1
1
0
0
1
1
0
0
1
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
V_CC (V)
0.0500
0.0375
0.0250
0.0125
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000
Catastrophic Thermal Protection
The processor supports the THERMTRIP# signal for catastrophic thermal protection. An
external thermal sensor should also be used to protect the processor and the system
against excessive temperatures. Even with the activation of THERMTRIP#, which halts
all processor internal clocks and activity, leakage current can be high enough that the
processor cannot be protected in all conditions without power removal to the processor.
If the external thermal sensor detects a catastrophic processor temperature of 125 °C
(maximum), or if the THERMTRIP# signal is asserted, the V_CC supply to the processor
must be turned off within 500 ms to prevent permanent silicon damage due to thermal
runaway of the processor. THERMTRIP# functionality is not guaranteed if the
PWRGOOD signal is not asserted.
Reserved and Unused Pins
All RESERVED (RSVD) pins must remain unconnected. Connection of these pins to V_CC,
V_SS, or to any other signal (including each other) may result in component malfunction
or incompatibility with future processors. See Section 4.2 for a pin listing of the
processor and the location of all RSVD pins.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if
AGTL+ termination is provided on the processor silicon. Unused active high inputs
should be connected through a resistor to ground (V_SS). Unused outputs can be left
unconnected.
The TEST1 and TEST2 pins must have a stuffing option of separate pull-down resistors
to V_SS.
For the purpose of testability, route the TEST3 and TEST5 signals through a ground-
referenced Zo = 55-Ω trace that ends in a via that is near a GND via and is accessible
through an oscilloscope connection.
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Datasheet