GMS87C4060 Datasheet, PDF (85/102 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

PRELIMINARY
GMS81C4040/87C4060
22. RESET
The GMS81C4040/GMS87C4060 have two types of reset
generation procedures; one is an external reset input, other
is a watch-dog timer reset. Table 22-1 shows on-chip hard-
ware initialization by reset action.
On-chip Hardware
Program counter
PC
RAM page register DPGR
G-flag of PSW
G
Initial Value
(FFFF_H) - (FFFE_H)
00_H
0
On-chip Hardware
Peripheral clock
Watchdog timer
Control registers
Initial Value
Off
Disable
Refer to Table 8-1 on page 22
Table 22-1 Initializing Internal Status by Reset Action
22.1 External Reset Input
The reset input is the RESET pin, which is the input to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin low for at least 8 oscillator periods, within the
operating voltage range and oscillation stable, a reset is ap-
plied and the internal state is initialized. After reset, 64ms
(at 4 MHz) add with 7 oscillator periods are required to
start execution as shown in Figure 22-2 .
Internal RAM is not affected by reset. When V_DD is turned
on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before reading or testing it.
When the RESET pin input goes high, the reset operation
is released and the program execution starts at the vector
address stored at addresses FFFE_H - FFFF_H.
A connecting for simple power-on-reset is shown in Figure
22-1 .
V_DD
+
−
GND
RESET
MCU
Figure 22-1 Simple Power-on-Reset Circuit
Oscillator
(X_IN pin)
RESET
Fetch
ADDRESS
BUS
DATA
BUS
1234567
?
??
?
FFFE FFFF Start
?
? ? ? FE ADL ADH OP
Stabilization Time
t_ST = 62.5mS at 4.19MHz
RESET Process Step
1
t_ST = _{fMAIN ÷1024} x 256
MAIN PROGRAM
Figure 22-2 Timing Diagram after RESET
Nov. 1999 Ver 1.0
PRELIMINARY
81