GMS87C4060 Datasheet, PDF (69/102 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

PRELIMINARY
GMS81C4040/87C4060
Bit
No.
Name
Function
SCL Frequency selection
SCL frequency = f_ex / (12 * CCR)
Value fex = 12MHz fex = 8MHz
0000 Not allowed Not allowed
0001 Not allowed Not allowed
0010 500.0KHz
333.3KHz
0011 333.3KHz
222.2KHz
3 CCR3 0100 250.0KHz
166.6KHz
2 CCR2 0101 200.0KHz
133.3KHz
1 CCR1 _{0110 166.6KHz}
0 CCR0 _{0111 142.9KHz}
111.1KHz
95.2KHz
1000 125.0KHz
83.3KHz
1001 111.1KHz
74.1KHz
1010 100.0KHz
66.6KHz
1011 90.0KHz
60.6KHz
1100 83.3KHz
55.5KHz
1101 76.4KHz
51.3KHz
1110 71.4KHz
47.6KHz
1111 66.6KHz
44.4KHz
Table 18-3 Bit function
RW RW
ICCR2 ACLK ACK 1
ADDRESS : 00DC_H
RESET VALUE : 000- 0000_b
RW RW RW RW
CCR3 CCR2 CCR1 CCR0
Figure 18-6 I²C control Register 2
SCL
PIN
I²C Request
Figure 18-7 Interrupt request signal generation timing
START condition generation
When the ESO bit of the I²C control register (00DB_H) is
“1”, writing to the I²C status register will generate START
condition. Refer to Figure 18-8 for the START condition
generation timing diagram.
ICSR write signal
(I²C status reg.)
SCL
SDA
BB (Bus busy) flag
t_SETUP
t_HOLD
t_BB
t_SETUP : Setup time
t_HOLD : Hold time
t_BB : Set time for BB
Figure 18-8 START condition generation timing
RESTART condition generation
RESTART condition’s setting sequence is as followings.
1. Write 020_H to I²C status register (ICSR, 00DA_H)
2. Write slave address to I²C data shift register (ICDR,
00D9_H)
3. Write 0F0_H to I²C status register (ICSR, 00DA_H)
STOP condition generation
Writing ‘C0h’ to ICSR will generate a stop condition,
Nov. 1999 Ver 1.0
PRELIMINARY
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