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GMS87C4060 Datasheet, PDF (78/102 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS
GMS81C4040/87C4060
PRELIMINARY
19.3 Multi Interrupt
If two requests of different priority levels are received si-
multaneously, the request of higher priority level is ser-
viced. If requests of the same priority level are received
simultaneously, an internal polling sequence determines
by hardware which request is serviced.
However, multiple processing through software for special
features is possible. Generally when an interrupt is accept-
ed, the I-flag is cleared to disable any further interrupt. But
as user set I-flag in interrupt routine, some further interrupt
can be serviced even if certain interrupt is in progress.
Main Program
service
TIMER 1
service
Occur
TIMER1 interrupt
enable INT0
disable other
EI
Occur
INT0
INT0
service
enable INT0
enable other
In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable "EI" in the TIMER1 routine.
Example: Even though Timer1 interrupt is in progress,
INT0 interrupt serviced without any suspend.
TIMER1:
PUSH
PUSH
PUSH
LDM
LDM
EI
:
:
:
A
X
Y
IENH,#80H
IENL,#0
;Enable INT0 only
;Disable other
;Enable Interrupt
:
:
:
LDM
LDM
POP
POP
POP
RETI
IENH,#FFH
IENL,#FEH
Y
X
A
;Enable all interrupts
Figure 19-7 Execution of Multi Interrupt
74
PRELIMINARY
Nov. 1999 Ver 1.0