GMS87C4060 Datasheet, PDF (38/102 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C4040/87C4060
PRELIMINARY
11. TIMER
11.1 Basic Interval Timer
The GMS81C4040/GMS87C4060 has one 8-bit Basic In-
terval Timer that is free-run and can not be stopped. Block
diagram is shown in Figure 11-1 .
The Basic Interval Timer generates the time base for
watchdog timer counting, and etc. It also provides a Basic
interval timer interrupt (BITIF). As the count overflow
from FF_H to 00_H, this overflow causes the interrupt to be
generated. The Basic Interval Timer is controlled by the
clock control register (CKCTLR) shown in Figure 11-2 .
Source clock can be selected by lower 3 bits of CKCTLR.
BITR and CKCTLR are located at same address, and ad-
dress 00D6_H is read as a BITR and written to CKCTLR..
PS4
PS5
PS6
PS7
PS8
PS9
PS10
PS11
f_ex÷2⁴
f_ex÷2⁵
f_ex÷2⁶
f_ex÷2⁷
f_ex÷2⁸
f_ex÷2⁹
f_ex÷2¹⁰
f_ex÷2¹¹
source
clock
MUX
8-bit up-counter
BITR
[0D6_H]
clear
Select Input clock ^{3 BITCK}
BTCL
Clock control register
[0D6_H]
CKCTLR
WDT
ON
ENPCK BTCL
BTS2
BTS1
BTS0
overflow
Internal bus line
BITIF _{Basic Interval Timer Interrupt}
Watchdog timer clock (WDTCK)
Figure 11-1 Block Diagram of Basic Interval Timer
BTS2~0
000
001
010
011
100
101
110
111
Source clock
Pre-Scaler output
PS4
PS5
PS6
PS7
PS8
PS9
PS10
PS11
f_ex÷2⁴
f_ex÷2⁵
f_ex÷2⁶
f_ex÷2⁷
f_ex÷2⁸
f_ex÷2⁹
f_ex÷2¹⁰
f_ex÷2¹¹
Table 11-1 Basic Interval Timer Interrupt Time
Interrupt
(overflow) Period
At f_ex=8MHz
0.512 mS
1.024
2.048
4.096
8.192
16.384
32.768
65.536
34
PRELIMINARY
Nov. 1999 Ver 1.0