GMS87C4060 Datasheet, PDF (30/102 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C4040/87C4060
PRELIMINARY
The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR
Example; Addressing accesses the address 0135_H regard-
less of G-flag and DPGR.
F100: 983501 INC!0135H
;A ←ROM[135H]
135_H
data
~~
0F100_H
98
0F101_H
35
0F102_H
01
Ã
~~ À
data+1 → data
þ
address: 0135
X indexed direct page, auto increment→ {X}+
In this mode, a address is specified within direct page by
the X register and the content of X is increased by 1.
LDA, STA
Example; G=0, X=35_H
F100: DB
LDA
{X}+
35_H
data
~~
0F100_H
DB
À
~~
data → A
þ ^{36H → X}
(5) Indexed Addressing
X indexed direct page (no offset) → {X}
In this mode, a address is specified by the X register.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA
Example; X=15_H, G=1, DPGR=03_H
E550: D4
LDA
{X};ACC←RAM[X].
315_H
data
~~
0E550_H
D4
À
~~
þ
data → A
X indexed direct page (8 bit offset) → dp+X
 ^{This address value is the second byte (Operand) of com-}
mand plus the data of -register. And it assigns the mem-
ory in Direct page.
ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA
STY, XMA, ASL, DEC, INC, LSR, ROL, ROR
Example; G=0, X=0F5_H
E550: C645
LDA
45H+X
3A_H
data
~~
0E550_H
C6
0E551_H
45
~~
þ
Ã
À ^{data → A}
45H+0F5H=13AH
26
PRELIMINARY
Nov. 1999 Ver 1.0