GMS87C4060 Datasheet, PDF (79/102 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

PRELIMINARY
GMS81C4040/87C4060
19.4 External Interrupt
The external interrupt on INT0, INT1... pins are edge trig-
gered depending the edge selection register.
Refer to “6. PORT STRUCTURES” on page 9.
The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, both edge.
INT0 pin
INT1 pin
INT0IF
INT0 INTERRUPT
INT1IF
INT1 INTERRUPT
INT2 pin
INT2IF
INT2 INTERRUPT
INT0, INT1 and INT2 are multiplexed with general I/O
ports. To use external interrupt pin, the bit of port function
register FUNC1 should be set to "1" correspondingly.
Response Time
The INT0, INT1 and INT2 edge are latched into INT0IF,
INT1IF and INT2IF at every machine cycle. The values
are not actually polled by the circuitry until the next ma-
chine cycle. If a request is active and conditions are right
for it to be acknowledged, a hardware subroutine call to the
requested service routine will be the next instruction to be
executed. For example, the DIV instruction takes twelve
machine cycles. Thus, a minimum of twelve complete ma-
chine cycles elapse between activation of an external inter-
rupt request and the beginning of execution of the first
instruction of the service routine
IEDS
[00F2_H]
Figure 19-8 External Interrupt Block Diagram
System clock
Instruction Fetch
1cycle
Last instruction execution (0~12cycle) Enter interrupt service routine (8cycle)
Interrupt request sampling
Interrupt overhaed (9~21cycle)
Figure 19-9 Interrupt Response Timing Diagram ( Interrupt overhead )
Nov. 1999 Ver 1.0
PRELIMINARY
75