GMS87C4060 Datasheet, PDF (80/102 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C4040/87C4060
PRELIMINARY
20. WATCHDOG TIMER
The watchdog timer rapidly detects the CPU malfunction
such as endless looping caused by noise or the like, and re-
sumes the CPU to the normal state.
The watchdog timer signal for detecting malfunction can
be selected either a reset CPU or a interrupt request.
When the watchdog timer is not being used for malfunc-
tion detection, it can be used as a timer to generate an in-
terrupt at fixed intervals.
Clock source
(BIT overflow : IFBIT)
clear
6-bit up-counter
WDT
comparator
IFWDT
Watchdog Timer interrupt
6-bit compare data
to reset CPU
WDTCL[bit6]
6
WDTR[bit5~0]
[00D7_H]
WDTR
Watchdog Timer Register
enable
[00D6_H]
WDTON[bit5]
CKCTLR
Clock control Register
Figure 20-1 Block Diagram of Watchdog Timer
Watchdog Timer Control
Figure 20-2 shows the watchdog timer control register.
The watchdog timer is automatically disabled after reset.
The CPU malfunction is detected as setting the detection
time, selecting output, and clearing the binary counter. Re-
peatedly clearing the binary counter within the setting de-
tection time.
If the malfunction occurs for any cause, the watchdog tim-
er output will become active at the rising overflow from
the binary counters unless the binary counter are cleared.
At this time, when WDTON=1 a reset is generated, which
drives the RESET pin low to reset the internal hardware.
When WDTON=0, a watchdog timer interrupt (IFWDT) is
generated.
CKTCLR
WDTR
ADDRESS : 00D6_H
RESET VALUE : 0000 0000_b
W
W
W
W
W
R
WDT
ON
ENP
CK
BTCL
BTS2
BTS1
BTS0
Watchdog timer On/Off control
0: Normal 6bit timer, Watchdog off
1: Watchdog timer
ADDRESS : 00D7_H
RESET VALUE : -011 1111_b
W
W
W
W
W
W
W
WDT
CL
W DTR5 ~ 0
Slave address
Watchdog timer Clear
0: Watchdog timer free run
1: Watchdog timer clear and free run
Automatically cleared this bit after 1cycle
Figure 20-2 Watchdog timer register
76
PRELIMINARY
Nov. 1999 Ver 1.0