GMS87C4060 Datasheet, PDF (41/102 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

PRELIMINARY
GMS81C4040/87C4060
TM0
00
T0CN
TDR0
Internal bus line
PS2
PS4
PS6 ^MUX
PS8
Timer 0
Clock
T0ST
Clear
TDR1
Timer 1
16bit Comparator
T1IF
Clock
Clear
Figure 11-5 Simplified Block Diagram of 16bit Timer0, 1
11.3 Timer / Event Counter 2, 3
Timer 2, 3 consists of prescaler, multiplexer, 8-bit compare
data register, 8-bit count register, Control register, and
Comparator as shown in Figure 11-5 .
These Timers have two operating modes. One is the timer
mode which is operated by internal clock, other is event
counter mode which is operated by external clock from pin
R25/EC2, R27/EC3.
These Timers can run separated 8bit timer or combined
16bit timer.
Note: You can read Timer 2, Timer 3 value from TDR2 or
TDR3. But if you write data to TDR2 or TDR3, it changes
Timer 2 or Timer 3 modulo data, not Timer value.
The content of TDR2, TDR3 must be initialized (by soft-
ware) with the value between 01_H and FF_H,not to 00_H.
Or not, Timer 2 or Timer 3 can not count up forever.
The control registers for Timer 2,3 are shown below
Timer mode register 2
ADDRESS : 00D1_H
RESET VALUE : -000 0000_b
RW RW RW RW RW RW RW
TM2
T3ST T3SL1 T3SL0 T2ST T2CN T2SL1 T2SL0
Timer 3 start
0: Count Hold
1: Count Clear and Start
Timer 3 input clock
Timer 2 input clock
00: PS2 (f_ex / 2²)
01: PS4 (f_ex / 2⁴)
10: PS6 (f_ex / 2⁶)
11: PS8 (f_ex / 2⁸)
00: Timer 2 overflow (16bit mode)
01: PS2 (f_ex / 2²)
10: PS4 (f_ex / 2⁴)
11: PS6 (f_ex / 2⁶)
Timer 2 start
0: Count Hold
Timer 2 control
0: Count Hold
1: Count Continue
1: Count Clear and Start
Timer 2 data register
ADDRESS : 00D4_H
RESET VALUE : Undefined
RW RW RW RW RW RW RW RW
TDR2
Timer 3 data register
ADDRESS : 00D5_H
RESET VALUE : Undefined
RW RW RW RW RW RW RW RW
TDR3
Port function select Register 1
W
W
W
ADDRESS : 00CE_H
RESET VALUE : -000 0000_b
W
W
W
W
FUNC1
EC3S EC2S INT4S INT3S INT2S INT1S INT0S
R27/EC3
0: R27
1: EC3
R25/EC2
0: R25
1: EC2
Nov. 1999 Ver 1.0
PRELIMINARY
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