GMS87C4060 Datasheet, PDF (28/102 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C4040/87C4060
PRELIMINARY
0D0H
TM0
R/W -0000000
0D1H
TM2
R/W -0000000
0D2H TDR0 R/W ????????
0D3H TDR1 R/W ????????
0D4H TDR2 R/W ????????
0D5H TDR3 R/W ????????
0D6H
BITR
R ????????
CKCTLR W --010111
0D7H WDTR
W -0111111
0D8H
ICAR
R/W 00000000
0D9H
ICDR
R/W 11111111
0DAH ICSR R/W 0001000-
0DBH ICCR1 R/W 00000000
0DCH ICCR2 R/W 00000000
0DEH SIOM R/W -0000001
0DFH SIOR R/W ????????
0E0H PWMR0 W ????????
0E1H PWMR1 W ????????
0E2H PWMR2 W ????????
0E3H PWMR3 W ????????
0E4H PWMR4 W ????????
0E5H PWMR5 W ????????
0E8H PWM8H R/W ????????
0E9H PWM8L R/W --??????
0EAH PWMCR1 R/W 00000000
0EBH PWMCR2 R/W --0-0000
0EEH
BUR
W ????????
0EFH
AIPS
W --000000
0F0H
0F1H
0F2H
0F3H
0F4H
0F5H
0F6H
0F7H
0F9H
0FAH
0FBH
0FCH
0FDH
ADCM
ADR
IEDS
IMOD
IENL
IRQL
IENH
IRQH
IDCR
IDFS
IDR
DPGR
TMR
R/W --011101
R ????????
W --000000
R/W --000000
R/W 0000000-
R/W 0000000-
R/W 00000000
R/W 00000000
R/W 0000-000
R 1----001
R ????????
R/W ----0000
W ????????
0AE0H OSDcon1 R/W 00000000
0AE1H OSDcon2 R/W -0000000
0AE2H OSDPOL W ????????
0AE3H FDWSET W 01111010
0AE4H EDGEcol W 10000111
0AE5H OSDLN R ---00000
0AE6H LHPOS W ????????
0AE8H SPVPOS W ????????
0AE9H SPHPOS W ????????
0AF0H L1ATTR W ????????
0AF1H L1VPOS W ????????
0AF3H L2ATTR W ????????
0AF4H L2VPOS W ????????
Table 8-1Control registers
byte
byte
byte, bit
byte, bit
byte, bit
byte, bit
byte
byte
byte
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte
byte
byte
byte
byte
byte
byte, bit
byte, bit
byte, bit
byte, bit
byte
byte
byte, bit
byte
byte
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte
byte
byte, bit
byte
byte, bit
byte, bit
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
byte
1. "byte, bit" means that register can be addressed by not only bit
but byte manipulation instruction.
2. "byte" means that register can be addressed by only byte
manipulation instruction. On the other hand, do not use any
read-modify-write instruction such as bit manipulation for clear-
ing bit.
24
PRELIMINARY
Nov. 1999 Ver 1.0