GMS87C4060 Datasheet, PDF (81/102 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

PRELIMINARY
GMS81C4040/87C4060
Example: Sets the watchdog timer detection time
LDM WDTR,#01??????b
Within WDT
detection time
Within WDT
detection time
LDM CKCTLR,#00111???b
LDM WDTR,#01??????b
:
:
:
:
LDM WDTR,#01??????b
:
:
:
:
LDM WDTR,#01??????b
;Clear Counter and set value(??????b)
;You have to set WDTR first, for prevent unpredictable interrupt
;when you set WDTON bit.
;Select clock source(???b) and WDTON=1
;Clear counter
;Clear counter
;Clear counter
Enable and Disable Watchdog
Watchdog timer is enabled by setting WDTON (bit 5 in
CKTCLR) to "1". WDTON is initialized to "0" during re-
set, WDTON should be set to "1" to operate after reset is
released.
Example: Enables watchdog timer reset
:
LDM CKTCLR,#001?????b ;WDTON←1
:
:
The watchdog timer is disabled by clearing bit 5 (WD-
TON) of CKTCLR.
Watchdog Timer Interrupt
The watchdog timer can also be used as a simple 6-bit tim-
er by clearing bit 5 (WDTON) of CKTCLR. The interval
of watchdog timer interrupt is decided by Basic Interval
Timer.
Interval equation is shown as below.
 =   ×    
The stack pointer (SP) should be initialized before using
the watchdog timer output as an interrupt source.
Example: 6-bit timer interrupt setting up.
LDX
TXSP
LDM
LDM
:
:
#03FH
;SP ← 3F
CKTCLR,#000?????b ;WDTON←0
WDTR,#01??????b ;WDTCL←0
Refer table and see BIT timer ().
CKCTLR
BTS2~0
BIT input
clock
Watchdog
timer input IFWDT cycle
clock
000_b
PS4 (2uS)
512uS
32,256uS
001_b
PS5 (4uS)
1,024uS
64,512uS
010_b
PS6 (8uS)
2,048uS 129,024uS
011_b PS7 (16uS) 4,096uS 258,048uS
100_b PS8 (32uS) 8,192uS 516,096uS
101_b PS9 (64uS) 16,384uS 1,032,192uS
110_b PS10 (128uS) 32,768uS 2,064,384uS
111_b PS11 (256uS) 65,536uS 4,128,768uS
Table 20-1 Watchdog timer MAX. cycle (Ex:f_ex=8MHz)
Nov. 1999 Ver 1.0
PRELIMINARY
77