GMS87C4060 Datasheet, PDF (37/102 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

PRELIMINARY
GMS81C4040/87C4060
10. CLOCK GENERATOR
As shown in Figure 10-1 , the clock generator produces the
basic clock pulses which provide the system clock to be
supplied to the CPU and the peripheral hardware. It con-
tains two oscillators: a main-frequency clock oscillator and
a sub-frequency clock oscillator. The system clock can
also be obtained from the external oscillator.
The clock generator produces the system clocks forming
clock pulse, which are supplied to the CPU and the periph-
eral hardware.
Main clock
3.6MHz
4MHz
8MHz
Minimum instruction cycle time
(ex:NOP ; f_ex 4clock is needed)
1,111nS
1,000nS
500nS
To the peripheral block, the clock among the not-divided
original clocks, divided by 2, 4,..., up to 1024 can be pro-
vided. Peripheral clock is enabled or disabled by bit 4 of
the peripheral clock enable register (ENPCK).
OSC
Circuit
f_EX
Internal system clock
Clock pulse Generator
ENPCK
[0D6_H]
CKCTLR
WDT
ON
ENPCK BTCL
BTS2
BTS1
BTS0
Clock control register
PRESCALER
Peripheral clock
Figure 10-1 Block Diagram of Clock Generator
Note: On the initial reset, all peripherals are run because
peripheral clock is supplied to each function block. If you
want to see more details, see Clock Control Register
(CKCTLR).
Clock control register
ADDRESS : 00D6_H
RESET VALUE : --01 0111_b
W
W
W
W
W
W
CKCTLR
WDT
ON
ENPCK BTCL
BTS2
BTS1
BTS0
Watch-dog
timer select
0: Normal 6bit timer
1: Watch-dog timer
Peri. Clock
0: Stop
1: Supply
B.I.T Clock
B.I.T set
0: Free run
1: B.I.T clear
Nov. 1999 Ver 1.0
PRELIMINARY
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