GMS87C4060 Datasheet, PDF (74/102 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C4040/87C4060
PRELIMINARY
Interrupt enable registers are shown in Figure 19-4 . These
registers are composed of interrupt enable flags of each in-
terrupt source, these flags determines whether an interrupt
will be accepted or not. When enable flag is "0", a corre-
sponding interrupt source is prohibited. Note that PSW
contains also a master enable bit, I-flag, which disables all
interrupts at once.
R/W
IRQH INT0
MSB
R/W R/W
OSD INT1
R/W
INT2
R/W R/W R/W R/W
T0 T2 1Frame VSync
LSB
ADDRESS: 00F7_H
INITIAL VALUE: 0000 0000_b
VSync interrupt request flag
1 Frame interrupt request flag
Timer / Counter 2 interrupt request flag
Timer / Counter 0 interrupt request flag
External interrupt 2 interrupt request flag
External interrupt 1 interrupt request flag
On screen display interrupt request flag
External interrupt 0 interrupt request flag
R/W R/W R/W R/W R/W R/W R/W
IRQL T1 T3 INTV WDT BIT SR I2C
MSB
ADDRESS: 00F5_H
INITIAL VALUE: 0000 000-_b
LSB
I²C interrupt request flag
Serial I/O interrupt request flag
Basic interval timer interrupt request flag
Watch-dog timer interrupt request flag
Interrupt interval measurement interrupt request flag (INT3/4)
Timer / Counter 3 interrupt request flag
Timer / Counter 1 interrupt request flag
Figure 19-3 Interrupt Request Flags
70
PRELIMINARY
Nov. 1999 Ver 1.0