GMS87C4060 Datasheet, PDF (43/102 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

PRELIMINARY
GMS81C4040/87C4060
TM2
00
T0CN
TDR2
Internal bus line
EC2
PS4
PS6 ^MUX
PS8
Timer 2
Clock
T0ST
Clear
TDR3
Timer 3
16bit Comparator
T3IF
Clock
Clear
Figure 11-8 Simplified Block Diagram of 16bit Timer/Event Counter 2,3
Timer Mode
In the timer mode, the internal clock is used for counting
up. Thus, you can think of it as counting internal clock in-
put. The contents of TDRn (n=0~3) are compared with the
contents of up-counter, Timer n. If match is found, a timer
n interrupt (TnIF) is generated and the up-counter is
cleared to 0. Counting up is resumed after the up-counter
is cleared.
 ^{As the value of TDRn is changeable by software, time in-}
terval is set as you want
Source clock
Start count
Up-counter
0
TDRn (n=0~3)
TnIF (n=0~3) interrupt
1
2
3
N
N-2 N-1 N 0 1
2
3
4
Match Counter
Detect Clear
Figure 11-9 Timer Mode Timing Chart
Event counter Mode
In event timer mode, counting up is started by an external
trigger. This trigger means falling edge of the ECn (n=2~3)
pin input. Source clock is used as an internal clock selected
with TM2. The contents of TDRn are compared with the
contents of the up-counter. If a match is found, an TnIF in-
terrupt is generated, and the counter is cleared to 00_H. The
counter is restarted by the falling edge of the ECn pin in-
put.
The maximum frequency applied to the ECn pin is f_ex/2
[Hz] in main clock mode.
In order to use event counter function, the bit EC2S, EC3
of the Port Function Select Register1 FUNC1(address
0CE_H) is required to be set to "1".
After reset, the value of TDRn is undefined, it should be
Nov. 1999 Ver 1.0
PRELIMINARY
39