GMS87C4060 Datasheet, PDF (73/102 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

PRELIMINARY
GMS81C4040/87C4060
INT0
IFOSD
INT1
INT2
Timer 0
Timer 2
1 Frame
IFVSync
Timer 1
Timer 3
Intr. interval
IFWDT
IFBIT
IFS
IFI2C
Internal bus line
IRQH
[0F7_H]
INT0
OSD
INT1
INT2
T0
T2
1Frame
VSync
T1
T3
INTV
WDT
BIT
SR
I2C
IRQL
[00F5_H]
IENH [00F6_H]
IENL [00F4_H]
Interrupt Enable
Register (Higher byte)
Interrupt Enable
Register (Lower byte)
Internal bus line
IMOD [00F3_H]
Bit5
RESET
BRK
To CPU
I Flag
Interrupt Master
Enable Flag
I-flag is in PSW , it is cleared by "D I", set by
"EI" instruction. W hen it goes interrupt service,
I-flag is cleared by hardw are, thus any other
interrupt are inhibited. W hen interrupt service is
completed by "R ETI" instruction, I-flag is set to
"1" by hardware.
Interrupt
Vector
Address
Generator
Figure 19-2 Block Diagram of Interrupt
Nov. 1999 Ver 1.0
PRELIMINARY
69