GMS87C4060 Datasheet, PDF (60/102 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C4040/87C4060
PRELIMINARY
and right side of character.
bit 7: DUSPCL
It controls sprite’s dot clock and scan line speed. It does not
affect to OSD. Sprite size is controlled as below.
DUSPCL
0
0
1
1
DUSP
0
1
0
1
Size
Normal
x2
Not used
x4
Table 17-2 Sprite pattern size
12x16
24x32
-
48x64
I/O Polarity ( initial ) Register
OSDPOL
W
POL
HS
W
POL
VS
W
POLI
W
POL
YM
ADDRESS : 0AE2_H
RESET VALUE : Undefined
W
W
W
W
POL _{POLB POLG POLR}
YS
POLHS : Hsync. input
POLVS : Vsync. input
POLI : Half intensity output
POLYM : Half blank output
POLB : Blue output
POLG : Green output
POLR : Red output
0: Active Low
1: Active High
OSD display enable,
include the edge color.
0: Off
1: On
Field detection Register
FDWSET
W
W
W
W
FMAX3 ~ 0
ADDRESS : 0AE3_H
RESET VALUE : 0111 1010_b
W
W
W
W
FPOL F M IN 2 ~ 0
Field detection
Maximum pointer
Field detection
Minimum pointer
Field detection polarity
0: Detect Odd field
Masking range : Min.~Max.
1: Detect Even field
Detecting range : Min.~Max.
Figure 17-4 OSD Registers - 2
OSDPOL
bit7~0 : POL HS, VS, I, YM, YS, B, G, R
It controls HS, VS, I, YM, YS, B, G, R port’s polarity. If
its value is 1, polarity is active high.
FDWSET
FDWSET (Field Detection Window Seting) register de-
tects the begin of VSync(Vertical Sync.) signal and distin-
guishs its current field is Even field or Odd field.
Ex1: VSync(Odd)
Ex2: VSync(Even)
HSync
FMIN
FMAX
Figure 17-5 FDWSET detection region
The region of FMIN[2:0] ~ FMAX[3:0] is field detection
window.
FMAX[3:0] can divide the region between HSync(Hori-
zontal Sync.) by 16. You can assume there is 4 bit horizon-
tal counter, for example HCOUNT[3:0] which count 0~15.
If the start of VSync is detected at the window, next field
is even. Else if VSync is detected another region of the
window, next field is odd.
It means start of VSync is detected during FMIN[2:0] <
HCOUNT[3:0] < FMAX[3:0] and FPOL value is 0, it dis-
tinguish odd field.
And, start of VSync is detected during FMIN[2:0] <
HCOUNT[3:0] < FMAX[3:0] and FPOL value is 1, it dis-
tinguish even field.
FMIN[2:0], FMAX[3:0] are compared with the horizontal
counter in OSD block.
56
PRELIMINARY
Nov. 1999 Ver 1.0