GMS87C4060 Datasheet, PDF (76/102 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C4040/87C4060
PRELIMINARY
19.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted
or the interrupt latch is cleared to "0" by a reset or an in-
struction. Interrupt acceptance sequence requires 8 f_ex (2
µs at f_MAIN=4MHz) after the completion of the current in-
struction execution. The interrupt service task terminates
upon execution of an interrupt return instruction [RETI].
Interrupt acceptance
1. The interrupt master enable flag (I-flag) is cleared to
"0" to temporarily disable the acceptance of any fol-
lowing maskable interrupts. When a non-maskable in-
terrupt is accepted, the acceptance of any following
interrupts is temporarily disabled.
2. Interrupt request flag for the interrupt source accepted
is cleared to "0".
3. The contents of the program counter (return address)
and the program status word are saved (pushed) onto
the stack area. The stack pointer decrements 3 times.
4. The entry address of the interrupt service program is
read from the vector table address, and the entry ad-
dress is loaded to the program counter.
5. The instruction stored at the entry address of the inter-
rupt service program is executed.
System clock
Instruction Fetch
Address Bus
PC
SP SP-1
SP-2
V.L. V.H.
New PC
Data Bus
Not used
PCH PCL PSW V.L. ADL ADH
OP code
Internal Read
Internal Write
Interrupt Processing Step
V.L. and V.H. are vector addresses.
ADL and ADH are start addresses of interrupt service routine as vector contents.
Interrupt Service Task
Figure 19-5 Interrupt Service routine Entering Timing
72
PRELIMINARY
Nov. 1999 Ver 1.0