GMS87C4060 Datasheet, PDF (66/102 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C4040/87C4060
PRELIMINARY
18. I²C Bus Interface
The I²C Bus interface circuit is shown in Figure 18-1 .
The multi-master I²C Bus interface is a serial communica-
tions circuit, conforming to the Phlips I²C Bus data trans-
fer format. This interface, offering both arbitration lost
detection and a synchronous functions, is useful for the
multi-master serial communications.
This multi-master I²C Bus interface circuit consists of the
I²C address register, the I²C data shift register, the I²C
clock control register, the I²C control register, the I²C sta-
tus register and other control circuits.
The more details about registers are shown Figure 18-2 ~
Figure 18-6 .
SDA
SCL
Noise
Elimination
Circuit
Noise
Elimination
Circuit
ICAR [D8_H] ^{SAD6 SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 R/W}
Address
comparator
ICDR [D9_H] ^{D7 D6 D5 D4 D3 D2 D1 D0}
Interrupt
Generation
Circuit
IFI2CR
Data
Control
Circuit
BB
Circuit
ICSR [00DA_H] ^{MST TRX BB PIN AL AAS AD0 LRB}
Clock
Control
Circuit
AL
Circuit
ICCR1 [00DB_H] ^{B S EL1~ 0}
ALS ESO
BC 2~0
ICCR2 [DC_H] ^{ACLK ACK 1}
CC R 3~0
Bit counter
External clock
Clock division
Figure 18-1 Block Diagram of multi-master I²C circuit
Control
The GMS81C4040/GMS87C4060 contains two I²C Bus
interface modules. It supports multi-master function, so it
contains arbitration lost detection, synchronization func-
tion,etc.
ITEM
Function
Format
Philips I²C standard
7bit addressing format
Communication
mode
Master transmitter
Master receiver
Slave transmitter
Slave receiver
ITEM
SCL clock
frequency
Function
66.6KHz ~ 500KHz (f_ex=12MHz)
44.4KHz ~ 333.3KHz (f_ex=8MHz)
I²C address register
It contains slave address (7bit) which is used during slave
mode and Read/Write bit.
Bit 7 ~ 0 : Slave address 6~0
Note: Bit 7~0 (SAD6~0) store slave address. The address
data transmitted from the master is compared with the con-
tents of these bits.
62
PRELIMINARY
Nov. 1999 Ver 1.0