GMS87C4060 Datasheet, PDF (67/102 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

PRELIMINARY
GMS81C4040/87C4060
ICAR
ADDRESS : 00D8_H
RESET VALUE : 0000 0000_b
RW RW RW RW RW RW RW R
SAD6 SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 R/W
Slave address
Figure 18-2 I²C address Register
I²C data shift register [ICDR]
The I²C data shift register is an 8bit shift register to store
received data and write transmit data.
When transmit data is written into this register, it is trans-
fered to the outside from bit7 in synchronization with the
SCL clock, and each time one-bit data is output, the data of
this register are shifted one bit to the left. When data is re-
ceived, it is input to this register from bit0 in synchroniza-
tion with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.
The I²C data shift register is in a write enable status only
when the ESO bit of the I²C control register (address
00DC_H) is “1”. The bit counter is reset by a write instruc-
tion to the I²C data shift register. Reading data from the
I²C data shift register is always enabled regardless of the
ESO bit value.
ICDR
ADDRESS : 00D9_H
RESET VALUE : 0000 0000_b
RW RW RW RW RW RW RW RW
D7 D6 D5 D4 D3 D2 D1 D0
Shift left 1-bit each S CL
Figure 18-3 Data shift register
I²C status register
The I²C status register controls the I²C Bus interface sta-
tus. The low-order 4bits are read only bits and the high-or-
der 4bits can be read out and written to.
The more details about its bits are shown Table 18-1.
Bit
No.
Name
Function
00: Slave / Receiver mode
01: Slave / Transmitter mode
10: Master / Receiver mode
11: Master / Transmitter mode
MST is cleared when
- After reset.
- After the arbitration lost is occured and
1 byte data transmission is finished.
7 MST - After stop condition is detected.
6 TRX - When start condition is disabled by
start condition duplication preventation
function.
TRX is cleared when
- After reset.
- When arbitration lost or stop condition
is occured .
- When MST is ‘0’, and start condition
or ACK non-return mode is detected.
BB(Bus busy)bit is 1 during bus is busy.
5
BB
This bit can be written by S/W. its value
is ‘1’ by start condition, and cleared by
stop condition.
PIN(Pending Interrupt Not)bit is inter-
rupt request bit.
If I²C interrupt request is issued, its
value is 0.
PIN is cleared when
- After 1 byte trasmission / receive is fin-
ished.
4 PIN PIN is set when
- After reset.
- After write instruction is excuted into
I²C data shift register ICDR.
- When PIN bit low, the output of SCL is
pulled down, So if you want to release
SCL, you must perform write instruction
CDR.
3
AL ^{Arbitration lost detection flag.}
If arbitration lost is detected, AL=1, or 0.
Slave address comparison flag.
It shows compared result with received
2 AAS _{address data and I}²_{C address register}
(ICAR).
It is 1, when two of data is same.
Table 18-1 Bit function
Nov. 1999 Ver 1.0
PRELIMINARY
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