GMS87C4060 Datasheet, PDF (54/102 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C4040/87C4060
PRELIMINARY
Interrupt interval determination
control Register
RW RW RW RW
ADDRESS : 00F9_H
RESET VALUE : 0000 -000_b
RW RW RW
IDCR
FCLR IMS I34H I34L
ISEL IDCK IDST
Counter control
See Figure 15-3
0: stop
Int. occuring time
1: Clear & count
0: Every selected
edge by I34H/L
1: Every FIFO 4level
is filled
Sampling clock select
0: PS9
1: PS8
FIFO clear is filled
External Interrupt select
0: Ignored
0: INT3
1: Clear and return to 0 1: INT4
Interrupt interval determination
FIFO status Register
R
ADDRESS : 00FA_H
RESET VALUE : 1--- -001_b
R
R
R
IDFS
DPO L
FOE FFUL FEMP
Data polarity
0: Data is stored every Falling edge
1: Data is stored every Rising edge
FIFO overrun error flag
0: No Error
1: Error detected
FIFO Empty flag
0: Data filled
1: Empty
FIFO Full flag
0: Not full
1: Full
Interrupt interval determination
FIFO Data Register
R
R
R
R
IDR
D7 D6 D5 D4
ADDRESS : 00FB_H
RESET VALUE : Undefined
R
R
R
R
D3 D2 D1 D0
Interrupt input





Item
Symbol
I34H
I34L
Detecting
edge


Frame Cycle


Pulse width

1
0
Rising
edge
0
1
Falling
edge
1
1 Both edge
1
1 Both edge
Figure 15-3 Setting for measurement
Port function select Register 1
W
W
W
ADDRESS : 00CE_H
RESET VALUE : -000 0000_b
W
W
W
W
FUNC1
EC3S EC2S INT4S INT3S INT2S INT1S INT0S
R26/INT4
0: R26
1: INT4
R24/INT3
0: R24
1: INT3
Figure 15-2 Int. interval measurement Registers
1) FIFO storing mechanism
FEMP=1, FFUL=0
FEMP=0, FFUL=0
Data 1
2) FIFO reading mechanism
Read out
FEMP=0
Data 1
Data 2
Data in
Read out _FEMP=0
Data 2
FEMP=0, FFUL=0
Data 1
Data 2
Data in
FEMP=1
FEMP=0, FFUL=1
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data in
FEMP=0, FFUL=1
Data 1
Data 2
Data 3
Data 4
Data 5
Data 7
Data in
Data 6 will be erased.
FOE=1 (Over run error)
Figure 15-4 Example for FIFO operating mechanism
50
PRELIMINARY
Nov. 1999 Ver 1.0