GS4911B_09 Datasheet, PDF(91/119 Page) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

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GS4911B_09 Datasheet, PDF (91/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

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Table 3-13: Configuration and Status Registers (Continued)

PCLK1_Phase/Divide

PCLK2_Phase/Divide

Address

2Ch

2Dh

Bit

15-7

5-2

15-7

5-2

Description

R/W

Reserved. Set these bits to zero when writing to

2Ch.

Current_P1 - selects the current drive capability of R/W

the PCLK1 pin. Set this bit HIGH for high current

drive. Otherwise, the current drive will be low.

NOTE: The current drive should be set high if PCLK1

is greater than 100MHz.

Reference: Section 3.7.1 on page 61

PCLK1_Phase - adjusts the output phase of the

R/W

PCLK1 clock with respect to the timing output pins.

Phase is delayed in 700ps (nominal) increments as

shown in Table 3-6.

Reference: Section 3.7.1 on page 61

Divide_By_4 - set this bit HIGH to divide the output R/W

PCLK1 by four.

NOTE: Setting this bit and bit 0 simultaneously HIGH

will hold the PCLK1 pin LOW.

Reference: Section 3.7.1 on page 61

Divide_By_2 - set this bit HIGH to divide the output R/W

PCLK1 by two.

NOTE: Setting this bit and bit 1 simultaneously HIGH

will hold the PCLK1 pin LOW.

Reference: Section 3.7.1 on page 61

Reserved. Set these bits to zero when writing to

2Dh.

Current_P2 - selects the current drive capability of R/W

the PCLK2 pin. Set this bit HIGH for high current

drive. Otherwise, the current drive will be low.

NOTE: The current drive should be set high if PCLK2

is greater than 100MHz.

Reference: Section 3.7.1 on page 61

PCLK2_Phase - adjusts the output phase of the

R/W

PCLK2 clock with respect to the timing output pins.

Phase is delayed in 700ps (nominal) increments as

shown in Table 3-6.

Reference: Section 3.7.1 on page 61

Divide_By_4 - set this bit HIGH to divide the output R/W

PCLK2 by four.

NOTE: Setting this bit and bit 0 simultaneously HIGH

will hold the PCLK2 pin LOW.

Reference: Section 3.7.1 on page 61

Divide_By_2 - set this bit HIGH to divide the output R/W

PCLK2 by two.

NOTE: Setting this bit and bit 1 simultaneously HIGH

will hold the PCLK2 pin LOW.

Reference: Section 3.7.1 on page 61

Default

GS4911B/GS4910B HD/SD/Graphics Clock and Timing

Generator with GENLOCK

Data Sheet

36655 - 5

June 2009

91 of 119

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