GS4911B_09 Datasheet, PDF (56/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

Alternatively, depending on the information available, the user may program the
Output_H_Reset register (address 17h) instead of programming registers 18h and 19h.
Output_H_Reset defines the denominator of the ratio of the output line frequency to the
input line frequency. Before Output_H_Reset is programmed, the numerator and
denominator must be reduced to their lowest factors.
For example, to genlock the output standard 720p/59.94 at 74.25/1.001MHz to the input
standard 525i/29.97 at 27MHz:
Input Line Frequency = ^I--ⁿ---^p---^u---^t----^V---ⁱ--^d---^e---^o----^C----^l--^o---^c---^k----^F---^r---^e--^q---^u---^e---ⁿ---^c---^y- = ^{2---7----0---0--0---0---0---0--}
Video Clocks per Input H
1716
Ouput Line Frequency
=
-^O-----^u----^t--^p----^u----^t----^V----ⁱ--^d---^e--^o-----^C----^l--^o---^c--^k-----^F---^r---^e--^q---^u---^e---ⁿ---^c---^y-
Video Clocks per Output H
=
7---4---2---5---0---0----0---0- _× 1---0----0--0--
1650 1001
∴^O-----^u---^t-^p---^u----^t---^L---ⁱ--ⁿ---^e----^F----^r--^e---^q---^u---^e--ⁿ---^c---^y-
Input Line Frequency
=
7---4---2---5---0---0----0---0----×_{-----1---0---0---0----}×_{-----1---7---1---6--}
27000000 × 1001 × 1650
=
2---0--
7
Therefore, program Output_H_Reset = 7. The numerator does not have to be
programmed.
NOTE: Either register 17h OR registers 18h and 19h should be programmed.
Programming all three registers will trigger two counter resets.
Programming OUTPUT_FV_RESET is preferred in all cases except where a custom
reference pulse is used in VID_STD[5:0] = 62 (see Section 3.10.1 on page 75). In this case,
OUTPUT_H_RESET must be used.
3.6.2.2 Programming the Internal Audio Genlock Block (GS4911B only)
By default, the audio clocks are always genlocked to the output video clock. However, if
a custom video or audio clock is programmed in the host interface (see Section 3.9 on
page 72), the user must manually program the internal audio genlock block.
A simplified version of the GS4911B’s internal audio genlock block is shown in
Figure 3-7.
27MHz
Internal Audio Genlock Block
Output Video
Clock
(fout
A_Reference_Divide
(host address 3Dh - 3Eh)
Phase
Comparator
Clock
Synthesizer
A_Feedback_Divide
(host address 3Bh - 3Ch)
Integer Multiple of
the Fundamental
Audio Sampling Clock
(n_*fs
Figure 3-7: Internal Audio Genlock Block
To genlock the audio clock to the video clock, the user must lock the fundamental
sampling frequency (f_s) to the frequency of the output video clock (f_out). This is
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
56 of 119