GS4911B_09 Datasheet, PDF (81/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

Table 3-13: Configuration and Status Registers (Continued)
Register Name
H_16_Period
V_Lines
V_2_Lines
F_Lines
Address
0Bh
0Ch
0Dh
0Eh
Bit
15-0
15-0
15-0
15-0
Description
R/W
Contains the number of 27MHz pulses in 16 H Sync R
periods. This register is set by the Reference Format
Detector block using the H Sync signal present on
the external HSYNC input pin. It is useful for 1/1.001
data detection.
NOTE: If the reference is removed this register will
remain unchanged until a new reference with a
different HSYNC period is applied.
Reference: Section 3.5.1 on page 45
Contains the number of H Sync periods in the input R
V Sync interval. This register is set by the Reference
Format Detector block using the signals present on
the external HSYNC and VSYNC input pins.
NOTE: If the reference is removed this register will
remain unchanged until a new reference with a
different VSYNC period is applied.
Reference: Section 3.5.1 on page 45
Contains the number of H Sync periods in 2 V Sync R
intervals. This register is set by the Reference
Format Detector block using the signals present on
the external HSYNC and VSYNC input pins.
NOTE: If the reference is removed this register will
remain unchanged until a new reference with a
different VSYNC period is applied.
Reference: Section 3.5.1 on page 45
Contains the number of H Sync periods in the input R
F Sync interval. This register is set by the Reference
Format Detector block using the signals present on
the external HSYNC and FSYNC input pins.
NOTE: If the reference is removed this register will
remain unchanged until a new reference is applied.
If the new reference does not include an FSYNC
pulse, this register will be set to zero.
Reference: Section 3.5.1 on page 45
Default
N/A
N/A
N/A
N/A
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
81 of 119