GS4911B_09 Datasheet, PDF (108/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

Table 3-13: Configuration and Status Registers (Continued)
Register Name
V_Start_4
V_Stop_4
Operator_Polarity_4
Address
68h
68h
69h
69h
6Ah
6Ah
6Ah
6Ah
6Ah
Bit
15
14-0
15
14-0
15-4
3
2
1
0
Description
R/W
Reserved. Set this bit to zero when writing to 68h. –
The value programmed in this register indicates the R/W
start line number of the leading edge of the
user-programmed V Sync signal USER4_V. For
interlaced output standards, this value corresponds
to the odd field line number.
NOTE: The value programmed in this register must
be less than the value programmed in V_Stop_4.
Reference: Section 3.8.3 on page 69
Reserved. Set this bit to zero when writing to 69h. –
The value programmed in this register indicates the R/W
end line number of the trailing edge of the
user-programmed V Sync signal USER4_V. For
interlaced output standards, this value corresponds
to the odd field line number.
NOTE: The value programmed in this register must
not exceed the maximum number of lines per field
of the outgoing standard.
Reference: Section 3.8.3 on page 69
Reserved. Set these bits to zero when writing to
–
6Ah.
Polarity_4 - Use this bit to invert the polarity of the R/W
final USER4 signal.
By default, the polarity of the user programmed
signals is active LOW. The polarity may be switched
to active HIGH by setting this bit LOW.
Reference: Section 3.8.3 on page 69
AND_4 - logical operator: USER4_H AND USER4_V R/W
Set this bit HIGH to output a signal that is only
active when both USER4_H and USER4_V are active.
When this bit is HIGH, bit 1 and bit 0 of this register
will be ignored.
Reference: Section 3.8.3 on page 69
OR_4 - logical operator: USER4_H OR USER4_V
R/W
Set this bit HIGH to output a signal that is active
whenever USER4_H or USER4_V are active.
When this bit is HIGH bit 0 of this register will be
ignored.
Reference: Section 3.8.3 on page 69
XOR_4 - logical operator: USER4_H XOR USER4_V
R/W
Set this bit HIGH to output a signal with the
following attributes: Signal becomes active when
either USER4_H or USER4_V is active. Signal is
inactive when USER4_H and USER4_V are both
active or both inactive.
Reference: Section 3.8.3 on page 69
Default
–
0
–
0
–
1
0
0
0
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
108 of 119