GS4911B_09 Datasheet, PDF (42/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

Figure 3-2 summarizes the differences in output accuracy in each mode of operation.
Assuming a crystal reference of +/-100ppm, in Free Run mode the frequency of the
output clock and timing signals will be as accurate as the crystal. In Genlock mode the
frequency will be as accurate as the input reference regardless of the crystal accuracy.
In Freeze mode, the frequency of the output clock and timing signals will be maintained
to within +/- 2ppm.
Assumption: Reference
XTAL is 27MHz+/-100ppm
+t
t
+100ppm
74.25 MHz
-100ppm
-t
+t
+2ppm
-2ppm
-t
Free Run
No Input
Reference
Genlock
Reference
Applied
Freeze
Reference
Lost
Time
NOTES:
1. t represents the temperature variability of the crystal
2. Diagram not to scale.
Figure 3-2: Output Accuracy and Modes of Operation
3.3 Output Timing Format Selection
At device power-up (described in Section 3.14 on page 111), the application layer should
immediately set the external VID_STD[5:0] and ASR_SEL[2:0] pins. The VID_STD[5:0]
pins are used to select a pre-programmed output video format, or to indicate that custom
timing parameters will be programmed in the host interface. The ASR_SEL[2:0] pins are
only available on the GS4911B, and are used to select the fundamental audio frequency
or to turn off audio clock generation.
The output timing formats selectable by the user via the VID_STD[5:0] pins are listed in
Section 1.4 on page 20. Table 3-7 in Section 3.7.2 on page 63 lists the audio sample rates
available via the ASR_SEL[2:0] pins.
If the user sets VID_STD[5:0] =1-51 on power-up, the device will first check the status of
the GENLOCK pin. If GENLOCK is set LOW and a valid reference has been applied to the
inputs, the device will output the selected video standard while attempting to genlock.
However, if a reference signal has not been applied and GENLOCK=LOW, the initial
clock and timing outputs may be determined by the internal default settings of the chip.
If GENLOCK is set HIGH, the device will immediately enter Free Run mode and will
correctly output the selected video standard.
If the user sets VID_STD[5:0] = 62 on power-up, the device will be configured to generate
custom output timing signals. The initial output timing signals will be equal to the
internal default timing of the chip until the user programs registers 4Eh to 55h of the host
interface (see Section 3.10 on page 74). Additionally, the output video clock will run at a
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
42 of 119