GS4911B_09 Datasheet, PDF(107/119 Page) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

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GS4911B_09 Datasheet, PDF (107/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

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Table 3-13: Configuration and Status Registers (Continued)

Operator_Polarity_3

H_Start_4

H_Stop_4

Address

65h

66h

67h

Bit

15-4

15-0

Description

R/W

Reserved. Set these bits to zero when writing to

65h.

Polarity_3 - Use this bit to invert the polarity of the R/W

final USER3 signal.

By default, the polarity of the user programmed

signals is active LOW. The polarity may be switched

to active HIGH by setting this bit LOW.

Reference: Section 3.8.3 on page 69

AND_3 - logical operator: USER3_H AND USER3_V R/W

Set this bit HIGH to output a signal that is only

active when both USER3_H and USER3_V are active.

When this bit is HIGH, bit 1 and bit 0 of this register

will be ignored.

Reference: Section 3.8.3 on page 69

OR_3 - logical operator: USER3_H OR USER3_V

R/W

Set this bit HIGH to output a signal that is active

whenever USER3_H or USER3_V are active.

When this bit is HIGH bit 0 of this register will be

ignored.

Reference: Section 3.8.3 on page 69

XOR_3 - logical operator: USER3_H XOR USER3_V

R/W

Set this bit HIGH to output a signal with the

following attributes: Signal becomes active when

either USER3_H or USER3_V is active. Signal is

inactive when USER3_H and USER3_V are both

active or both inactive.

Reference: Section 3.8.3 on page 69

The value programmed in this register indicates the R/W

pixel start point for the leading edge of the

user-programmed H Sync signal USER4_H.

NOTE: The value programmed in this register must

be less than the value programmed in H_Stop_4.

Reference: Section 3.8.3

The value programmed in this register indicates the R/W

pixel end point for the trailing edge of the

user-programmed H Sync signal USER4_H.

NOTE: The value programmed in this register must

not exceed the maximum number of clock periods

per line of the outgoing standard.

Reference: Section 3.8.3 on page 69

Default

GS4911B/GS4910B HD/SD/Graphics Clock and Timing

Generator with GENLOCK

Data Sheet

36655 - 5

June 2009

107 of 119

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