GS4911B_09 Datasheet, PDF (101/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

Table 3-13: Configuration and Status Registers (Continued)
Register Name
Vsync_To_Last_Active_Line
Address
55h
Bit
15-0
Description
R/W
Contains the number of lines from the start of V
R/W
Sync to the end of active video for the selected
output timing format.
This register is 15.1 encoded (i.e. bit 0 represents
'0.5' when set HIGH and '0' when set LOW).
If VID_STD[5:0] = 62, this register may be set by the
user when programming custom output timing
signals. Otherwise, this register is read-only.
NOTE: The user cannot specify a custom vertical
blanking signal to end in the middle of a line. If this
occurs, the device will automatically adjust the
timing of the signal to fall at the beginning of the
next line.
Reference: Section 3.10 on page 74
Default
–
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
101 of 119