GS4911B_09 Datasheet, PDF(82/119 Page) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

GS4911B_09 Datasheet, PDF (82/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

◁

Table 3-13: Configuration and Status Registers (Continued)

Input_Standard

Address

0Fh

Amb_Std_Sel

10h

Reference_Standard_Disable 14h-11h

Bit

15-13

11-6

5-0

15-11

10-0

63-0

Description

R/W

Reserved. Set these bits to zero when writing to

0Fh.

Force_Input - Set this bit HIGH to force the

R/W

GS4911B/GS4910B to recognize the applied input

reference format as the standard programmed in

bits 11-6 of this register.

Reference: Section 3.2.1.2 on page 41

Forced_Standard - When bit 12 is set HIGH, the

R/W

GS4911B/GS4910B will use the value programmed in

these bits, rather than the value in bits 5-0, to

determine the input reference format. The 6-bit

value programmed here should always correspond

to the VID_STD[5:0] value of the applied reference.

These bits should only be programmed as part of

the Freeze mode procedure described in

Section 3.2.1.2 on page 41.

Detected_Standard - Contains the video standard

R/W

applied to the input reference pins once it has been

detected. These bits are set by the Reference

Format Detector block and correspond to the

VID_STD[5:0] value of the standard as listed in

Table 1-2.

The Detected_Standard bits will be set to zero if no

input reference signal is applied or if the input

reference signal is not an automatically recognized

video format. Otherwise the value will be between

1 and 54.

Reference: Section 3.5.2 on page 46

Reserved. Set these bits to zero when writing to

10h.

The user may set this register to distinguish

R/W

between different formats that look identical to the

internal Reference Format Detector block. See

Table 3-2.

Reference: Section 3.5.2.1 on page 46

The Reference_Standard_Disable registers may be R/W

used to disable one or more of the recognized input

standards from being used to genlock the output.

This is done by setting the bit HIGH that

corresponds to the VID_STD[5:0] value of the video

standard in Table 1-2.

For example, if bit 5 is set HIGH, then the output

clock and timing signals will not genlock to an input

reference with timing corresponding to

VID_STD[5:0] = 5 in Table 1-2.

Address 11h = bits 15-0

Address 12h = bits 31-16

Address 13h = bits 47-32

Address 14h = bits 63-48

Reference: Section 3.6 on page 50

Default

N/A

GS4911B/GS4910B HD/SD/Graphics Clock and Timing

Generator with GENLOCK

Data Sheet

36655 - 5

June 2009

82 of 119

▷