GS4911B_09 Datasheet, PDF (110/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

3.13 JTAG
When the JTAG/HOST input pin of the GS4911B/GS4910B is set HIGH, the host interface
port will be configured for JTAG test operation. In this mode, pins 57 through 60 become
TCLK, TDI, TDO, and TMS. In addition, the RESET pin will operate as the test reset pin.
Boundary scan testing using the JTAG interface will be enabled in this mode.
There are two methods in which JTAG can be used on the GS4911B/GS4910B:
1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test
Equipment) during PCB assembly; or
2. Under control of the host for applications such as system power on self tests.
When the JTAG tests are applied by ATE, care must be taken to disable any other devices
driving the digital I/O pins. If the tests are to be applied only at ATE, this can be
accomplished with high-impedance buffers used in conjunction with the JTAG/HOST
input signal. This is shown in Figure 3-19.
Application HOST
GS4911B/GS4910B
CS_TMS
SCLK_TCLK
SDIN_TDI
SDOUT_TDO
JTAG/HOST
Figure 3-19: In-Circuit JTAG
In-circuit ATE probe
Alternatively, if the test capabilities are to be used in the system, the host may still
control the JTAG/HOST input signal, but some means for tri-stating the host must exist
in order to use the interface at ATE. This is represented in Figure 3-20.
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
110 of 119