GS4911B_09 Datasheet, PDF(54/119 Page) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

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GS4911B_09 Datasheet, PDF (54/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

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3.6.2 Manual Locking Process

Using the host interface, the GS4911B/GS4910B may be manually programmed to

genlock certain video formats and audio clocks that are not automatically genlocked by

the device. The following sections discuss when the user should manually program the

internal video and/or audio genlock block, and how these blocks are programmed.

3.6.2.1 Programming the Internal Video Genlock Block and Output Line/Frame Reset Registers

The user will be required to manually program the internal video genlock block and

output line/frame reset registers during any of the following situations:

1. The pre-programmed output format and input reference cannot be automatically

genlocked according to the cross-reference genlock table (Table 3-4 in Section 3.6.1

on page 50).

2. A custom video clock is programmed in the host interface (Section 3.9.1 on page 72).

3. VID_STD[5:0] = 62 and a custom H-based timing output signal is programmed (see

Section 3.10 on page 74).

4. VID_STD[5:0] = 62 and a custom reference pulse is applied to HSYNC (see

Section 3.10.1 on page 75).

Video Genlock Block Host Registers

A simplified version of the GS4911B/GS4910Bâs internal video genlock block is shown

in Figure 3-6.

27MHz

HSYNC

(fHref

Internal Video Genlock Block

H_Reference_Divide

(host address 2Ah - 2Bh)

Phase

Comparator

Clock

Synthesizer

Output Video

Clock

(fout

H_Feedback_Divide

(host address 28h - 29h)

Figure 3-6: Internal Video Genlock Block

To genlock the output clock and video timing signals to the input format, the user must

first lock the frequency of the output video clock (fout) to the frequency of the reference

pulse on HSYNC (fHref). This is accomplished by programming the set of integers

(H_Feedback_Divide, H_Reference_Divide) in the equation:

where:

fout = output video clock frequency

fHref = reference H pulse frequency on HSYNC

H_Feedback_Divide = numerator of the divide ratio (host register 28h-29h)

H_Reference_Divide = denominator of the divide ratio (host register 2Ah-2Bh)

GS4911B/GS4910B HD/SD/Graphics Clock and Timing

Generator with GENLOCK

Data Sheet

36655 - 5

June 2009

54 of 119

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