GS4911B_09 Datasheet, PDF (19/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

Table 1-1: Pin Descriptions (Continued)
Pin
Number
61
Name
RESET
Timing
Type
Non
Input
Synchronous
64
GENLOCK
Non
Input
Synchronous
–
Ground Pad
–
–
Description
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to their default
settings or to reset the JTAG test sequence.
Host Mode (JTAG/HOST = LOW):
When asserted LOW, all host registers and functional blocks will be
set to their default conditions. All input and output signals will
become high impedance, except PCLK1 and PCLK2, which will be set
LOW.
When set HIGH, normal operation of the device will resume.
The user must hold this pin LOW during power-up and for a
minimum of 500 uS after the last supply has reached its operating
voltage.
JTAG Test Mode (JTAG/HOST = HIGH):
When asserted LOW, all host registers and functional blocks will be
set to their default conditions and the JTAG test sequence will be
held in reset.
When set HIGH, normal operation of the JTAG test sequence will
resume.
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Selects Genlock mode or Free Run mode.
When this pin is set LOW and the device has successfully genlocked
the output to the input reference, the device will enter Genlock
mode. The video clock and timing outputs will be frequency and
phase locked to the detected reference signal.
When this pin is set HIGH, the video clock and the reference-timing
generator will free-run.
By default, the GS4911B’s audio clocks will be genlocked to the
output video clock regardless of the setting of this pin.
NOTE: The user must apply a reference to the input of the device
prior to setting GENLOCK = LOW. If the GENLOCK pin is set LOW
and no reference signal is present, the generated clock and timing
outputs of the device may correspond to the internal default
settings of the chip until a reference is applied.
Ground pad on bottom of package must be soldered to main
ground plane of PCB.
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
19 of 119