GS4911B_09 Datasheet, PDF (46/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

3.5.2 Input Reference Validity
Before the device attempts to operate in Genlock mode, the input signals applied to
HSYNC and VSYNC must be valid and must conform to one of the 36 recognized video
standards or 16 recognized graphics standards described in Section 1.4 on page 20.
Alternatively, if VID_STD[5:0] = 62, the device may be manually programmed to genlock
to a reference that is neither valid nor recognized (see Section 3.10.1 on page 75).
For an input reference signal to be considered valid, the periodicity of HSYNC must be
between 9us and 70us, and the periodicity of VSYNC must be between 8ms and 50ms.
The FSYNC signal is not essential for validity. For output video standards other than
VID_STD[5:0] = 62, the REF_LOST pin will be set LOW once the input reference signal is
considered valid.
If the input signal is valid, the device then compares the timing parameters of the input
reference signal to each of the 36 video and 16 graphics standards listed in Table 1-2,
and determines if the input reference is one of the recognized standards. If it is, the
VID_STD[5:0] value for the format is written to the Input_Standard register at address
0Fh of the host interface. If the input signal is invalid, or if the reference format is
unrecognized, 00h is programmed in this register.
Once a reference signal is valid and recognized by the device, VSYNC and FSYNC will
no longer be monitored. Loss of signal on these pins will not affect the operation of the
device.
If VID_STD[5:0] is not set to 62 and the REF_LOST pin is HIGH, or if the input signal is
valid, but unrecognized as one of the 36 video or 16 graphics formats, the GENLOCK pin
should not be set LOW.
If VID_STD[5:0] = 62, the REF_LOST output will reflect the presence of a stable signal
with a period of less than 2.4ms on the HSYNC input pin. This allows the user to program
the device to lock to a single input reference only
The REF_LOST output pin may also be read via bit 0 of the Genlock_Status register (see
Section 3.12.3 on page 79).
3.5.2.1 Ambiguous Standard Selection
There are some standards with identical H, V, and F timing parameters, such that the
GS4911B/GS4910B’s reference format detector cannot distinguish between them.
Table 3-2 groups standards with shared H, V, and F periods. Using the Amb_Std_Sel
register at address 10h of the host interface, the user may select their choice of standard
to be identified with a particular set of measurements. For example, to have 1716 clocks
of 27MHz per line with 525 lines per frame identified as 4fsc 525, program
Amb_Std_Sel[10:0] = XXX10XXXXXX, where ‘X’ signifies ‘don’t care’.
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
46 of 119