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GS4911B_09 Datasheet, PDF (88/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Video_Status
Nv
Address
1Fh
1Fh
1Fh
1Fh
1Fh
1Fh
21h-20h
Bit
15-5
4
3
2
1
0
31-0
Description
R/W
Reserved.
–
Ref_H_Polarity - status register to indicate the
R
detected H Sync polarity ('1' for positive, '0' for
negative).
This bit will be zero when no reference signal is
present.
Reference: Section 3.4.3 on page 45
Ref_V_Polarity - status register to indicate the
R
detected V Sync polarity ('1' for positive, '0' for
negative).
This bit will be zero when no reference signal is
present and for digital blanking input references.
Reference: Section 3.4.3 on page 45
Ref_Blank_Timing - status register to indicate the
R
input detection of H blanking vs. H sync timing (‘1’
for blanking, '0' for sync timing).
This bit will be zero when no reference signal is
present.
Reference: Section 3.4.3 on page 45
A_pll_Lock (GS4911B only)- this bit will be HIGH
R
when the generated audio clock is locked to the
video clock reference.
NOTE: This bit will remain high in the GS4910B.
Reference: bit 1 of register 15h.
V_pll_Lock - this bit will be HIGH when the
R
generated video clock is locked to the H Sync input
reference.
Reference: bit 1 of register 15h.
A non-zero number programmed in this register
R/W
defines the numerator for the ratio of the video
clock to the 27MHz reference.
This register can be used for creating custom video
clock frequencies.
NOTE: Once this register is programmed, it must be
updated using bit 6 of register 16h.
The default value of this register will vary
depending on the output video standard selected.
Address 20h = bits 15-0
Address 21h = bits 31-16
Reference: Section 3.9.1 on page 72
Default
–
N/A
N/A
N/A
N/A
N/A
–
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
88 of 119