GS4911B_09 Datasheet, PDF (16/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

Table 1-1: Pin Descriptions (Continued)
Pin
Number
42
43
45
46, 47
48
Name
Timing
Type Description
TIMING_OUT_7
TIMING_OUT_8
LVDS/PCLK3_VDD
PCLK3, PCLK3
LVDS/PCLK3_GND
Synchronous
with PCLK1
~ PCLK3
Output
TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio
timing (GS4911B only); USER_1~4.
See Section 1.5 on page 26 for signal descriptions.
NOTE: Default output is 10 Field ID (10FID).
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current
drive will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
Synchronous
with PCLK1
~ PCLK3
Output
TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio
timing (GS4911B only); USER_1~4.
See Section 1.5 on page 26 for signal descriptions.
NOTE: Default output is Display Enable (DE).
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current
drive will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
–
Power Most positive power supply connection for PCLK3 output circuitry
Supply and LVDS driver. Connect to +1.8V DC.
–
Output CLOCK SIGNAL OUTPUTS
Signal levels are LVDS compatible.
Differential video clock output signal.
PCLK3/PCLK3 present a differential video sample rate clock output
to the application layer.
By default, after system reset, this output will operate at the
fundamental frequency determined by the setting of the
VID_STD[5:0] pins. It is possible to define other non-standard
fundamental clock rates using the host interface.
It is also possible to select different division ratios for the
PCLK3/PCLK3 outputs by programming designated registers in the
host interface. A clock output of the fundamental rate,
fundamental rate ÷2, or fundamental rate ÷4 may be selected.
The PCLK3/PCLK3 outputs will be high impedance when
VID_STD[5:0] = 00h.
–
Power Ground connection for PCLK3 output circuitry and LVDS driver.
Supply Connect to GND.
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
16 of 119