GS4911B_09 Datasheet, PDF (103/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

Table 3-13: Configuration and Status Registers (Continued)
Register Name
H_Start_1
H_Stop_1
V_Start_1
V_Stop_1
Address
56h
56h
56h
57h
58h
59h
59h
5Ah
5Ah
Bit
2
1
0
15-0
15-0
15
14-0
15
14-0
Description
R/W
V_Sync - set this bit HIGH to invert the polarity of
R/W
the V Sync timing output signal.
By default, the V Sync signal is active LOW.
Reference: Table 1-3
H_Blanking - set this bit HIGH to invert the polarity R/W
of the H Blanking timing output signal.
By default, the H Blanking signal will be LOW for
the portion of the video line containing valid video
samples.
Reference: Table 1-3
H_Sync - set this bit HIGH to invert the polarity of
R/W
the H Sync timing output signal.
By default, the H Sync signal is active LOW.
Reference: Table 1-3
The value programmed in this register indicates the R/W
pixel start point for the leading edge of the
user-programmed H Sync signal USER1_H.
NOTE: The value programmed in this register must
be less than the value programmed in H_Stop_1.
Reference: Section 3.8.3 on page 69
The value programmed in this register indicates the R/W
pixel end point for the trailing edge of the
user-programmed H Sync signal USER1_H.
NOTE: The value programmed in this register must
not exceed the maximum number of clock periods
per line of the outgoing standard.
Reference: Section 3.8.3 on page 69
Reserved. Set this bit to zero when writing to 59h. –
The value programmed in this register indicates the R/W
start line number of the leading edge of the
user-programmed V Sync signal USER1_V. For
interlaced output standards, this value corresponds
to the odd field number.
NOTE: The value programmed in this register must
be less than the value programmed in V_Stop_1.
Reference: Section 3.8.3 on page 69
Reserved. Set this bit to zero when writing to 5Ah. –
The value programmed in this register indicates the R/W
end line number of the trailing edge of the
user-programmed V Sync signal USER1_V. For
interlaced output standards, this value corresponds
to the odd field number.
NOTE: The value programmed in this register must
not exceed the maximum number of lines per field
of the outgoing standard.
Reference: Section 3.8.3 on page 69
Default
0
0
0
0
0
–
0
–
0
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
103 of 119