GS4911B_09 Datasheet, PDF (45/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

10FID Input
Horizontal Sync Input
Total Line
Line 1, Frame 1 every 'n' frames
Line 1 every n frames where:
n = 5 @ 29.97 fps, 30 fps
n = 10 @ 59.94 fps, 60 fps
Figure 3-5: 10FID Input Timing
3.4.3 Automatic Polarity Recognition
To accommodate any standards that employ the polarity of the H and V sync signals to
indicate the format of the display, the GS4911B/GS4910B will recognize H and V sync
polarity and automatically synchronize to the leading edge.
The polarities of the HSYNC and VSYNC signals are reported in bits 3 and 4 of the
Video_Status register. Additionally, bit 2 of this register reports the detection of either
analog or digital input timing. See Section 3.12.3 on page 79 for detailed register
descriptions.
3.5 Reference Format Detector
The reference format detector checks the validity and analyzes the format of the input
reference signal. It is designed to accurately differentiate between 59.94 and 60Hz
frame rates.
3.5.1 Horizontal and Vertical Timing Characteristic Measurements
When a reference signal is applied to the designated input pins, the GS4911B/GS4910B
will analyse the signal and report the following in registers 0Ah to 0Eh of the host
interface:
• the number of 27MHz clock pulses between leading edges of the H input reference
signal (H_Period register)
• the number of 27MHz clock pulses in 16 horizontal periods (H_16_Period register)
• the number of H reference pulses between leading edges of the V input reference
signal (V_Lines register)
• the number of H reference pulses in two vertical periods (V_2_Lines register)
• the number of H reference pulses in one F period (F_Lines register)
These parameters may be read via the host interface and are used by the device to
determine reference signal validity.
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
45 of 119