GS4911B_09 Datasheet, PDF(62/119 Page) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

GS4911B_09 Datasheet, PDF (62/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

◁

23h. Please see Section 3.9 on page 72 for a detailed explanation of custom clock

generation.

Once the video clock has been generated, it will be presented to the application layer via

the PCLK1 to PCLK3 pins. By default, each of the 3 video clock outputs will produce the

generated fundamental clock frequency. However, it is possible to select other rates for

each PCLK output by programming the PCLK_Phase/Divide registers beginning at

address 2Ch of the host interface (see Section 3.12.3 on page 79).

Each PCLK output may be individually programmed to provide one of the following:

â¢ PCLK fundamental frequency

â¢ Fundamental frequency /2

â¢ Fundamental frequency /4

When all six VID_STD[5:0] pins are set LOW, the video clocks will be disabled. PCLK1

and PCLK2 will go LOW and PCLK3/PCLK3 will be high impedance.

NOTE: If the PCLK divider bits of registers 2Ch - 2Eh are set to enable a divide by 2 or

divide by 4, the resultant divided clock will align with the falling edge of the output H

Sync timing signal either on its rising or falling edge.

The PCLK1 to PCLK3 outputs may also be individually delayed with respect to the eight

TIMING_OUT signals to allow for skew control downstream from the

GS4911B/GS4910B. Using the PCLK_Phase/Divide registers, the phase of each clock

may be delayed up to a nominal 10.3ns in 16 steps of approximately 700ps each

(Table 3-6). This delay is available in addition to the genlock timing offset phase

adjustment described in Section 3.2.1 on page 38.

Table 3-6: Video Clock Phase Adjustment Host Settings

PCLKn_Phase[3:0] Setting

0 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh

Phase Increment (ns)

0 0.7 1.4 2.1 2.8 3.5 4.2 4.9 5.6 6.3 7.0 7.7 8.4 9.1 9.8 10.3

NOTES:

1. The phase increments listed above are nominal values.

2. The phase of PCLK is delayed relative to the TIMING_OUT pins.

Additionally, the current drive capability of PCLK1 and PCLK2 may be set high or low

using the PCLK_Phase/Divide registers. By default the current drive will be low. It must

be set high if the clock rate is greater than 100MHz.

GS4911B/GS4910B HD/SD/Graphics Clock and Timing

Generator with GENLOCK

Data Sheet

36655 - 5

June 2009

62 of 119

▷