GS4911B_09 Datasheet, PDF (51/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

If the device cannot automatically genlock the output to the applied reference, the
LOCK_LOST pin will be set HIGH and the device will operate in Free Run mode. In this
case, the user may program designated registers to manually allow locking to occur
(Section 3.6.2 on page 54).
Individual H, V, and F-locked signals can be read from the Genlock_Status register of the
host interface. Additionally, designated bits in the Genlock_Control register may be
configured to permit the genlock block to ignore invalid timing on the HSYNC, VSYNC,
or FSYNC pin when determining the locked status of the device. These registers are
described in Section 3.12.3 on page 79.
NOTE: When attempting to lock some output graphics standards to an input reference,
the device will automatically modify the output frame rate from the VESA standard to
permit cross-locking to occur. The exact change will depend on the output standard
selected and the input reference detected. Standards affected by this behaviour are
denoted by an 'a' or a 'b' suffix in Table 3-4.
VID_STD[5:0] = 62:
Setting VID_STD[5:0]=62 allows custom timing signals to be programmed in the host
register (see Section 3.10 on page 74). It has the additional feature of disabling the
validity check of the input reference signal.
The device will automatically attempt to genlock the custom output to the input using
the same process that is used when VID_STD[5:0] = 1 to 51. The user must manually
program the internal genlock block if a custom H-based timing output signal is
programmed or if a custom reference pulse is applied to HSYNC.
VID_STD[5:0] = 63:
When VID_STD[5:0]=63, the device will send the detected input reference timing
parameters to the clock synthesis and timing generator blocks. The device will produce
an output format with identical timing to the input reference. It will then lock the output
format to the reference, adjust the output timing parameters based on the genlock
timing offset registers (Section 3.2.1.1 on page 38), and set the LOCK_LOST pin LOW.
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
51 of 119