GS4911B_09 Datasheet, PDF (90/119 Pages) Gennum Corporation – HD/SD/Graphics Clock and Timing Generator with GENLOCK

Table 3-13: Configuration and Status Registers (Continued)
Register Name
Video_Cap_Genlock
Video_Res_Genlock
H_Feedback_Divide
H_Reference_Divide
Address
26h
26h
27h
27h
29h-28h
2Bh-2Ah
Bit
15-6
5-0
15-6
5-0
31-0
31-0
Description
Reserved. Set these bits to zero when writing to
26h.
Control signal to adjust loop bandwidth of video
genlock block.
The value programmed in this register must be
between 10 and Video_Res_Genlock - 21.
The default value of this register will vary
depending on the output video standard selected.
Reference: Section 3.6.4 on page 58
Reserved. Set these bits to zero when writing to
27h.
Control signal to adjust loop bandwidth of video
genlock block.
The value programmed in this register must be
between 32 and 42.
The default value of this register will vary
depending on the output video standard selected.
Reference: Section 3.6.4 on page 58
In the internal video genlock block, this register
defines the numerator of the divide ratio.
This register may be programmed to manually
genlock the output to the input reference.
The default value of this register will vary
depending on the output video standard selected.
Address 28h = bits 15-0
Address 29h = bits 31-16
Reference: Section 3.6.2.1 on page 54
In the internal video genlock block, this register
defines the denominator of the divide ratio.
This register may be programmed to manually
genlock the output to the input reference.
The default value of this register will vary
depending on the output video standard selected.
Address 2Ah = bits 15-0
Address 2Bh = bits 31-16
Reference: Section 3.6.2.1 on page 54
R/W
–
R/W
–
R/W
R/W
R/W
Default
–
–
–
–
–
–
GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
90 of 119