GS2961 Datasheet, PDF (9/104 Pages) Gennum Corporation – 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing

Table 1-1: Pin Descriptions (Continued)
Pin
Number
A5, A6, B5,
B6, C5, C6
A7, D10,
G10, K7
A8
Name
STAT[0:5]
IO_VDD
PCLK
Timing
Type
Description
Output
MULTI-FUNCTIONAL OUTPUT PORT.
Signal levels are LVCMOS/LVTTL compatible.
Each of the STAT [0:5] pins can be configured individually to output
one of the following signals:
Signal
H/HSYNC
V/VSYNC
F/DE
LOCKED
Y/1ANC
C/2ANC
DATA ERROR
EDH DETECTED
CARRIER DETECT
RATE_DET0
RATE_DET1
Default
STAT0
STAT1
STAT2
STAT3
STAT4
−
STAT5
−
−
−
−
Input Power POWER connection for digital I/O. Connect to 3.3V or 1.8V DC
digital.
Output
PARALLEL DATA BUS CLOCK
Signal levels are LVCMOS/LVTTL compatible.
3G 10-bit or 20-bit mode
PCLK @ 148.5 or 148.5/1.001MHz
HD 10-bit mode
PCLK @ 148.5 or 148.5/1.001MHz
HD 20-bit mode
PCLK @ 74.25 or 74.25/1.001MHz
SD 10-bit mode
PCLK @ 27MHz
SD 20-bit mode
PCLK @ 13.5MHz
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
9 of 104