GS2961 Datasheet, PDF (77/104 Pages) Gennum Corporation – 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing

Ancillary data packet extraction and deletion is disabled when the IOPROC_EN/DIS pin
is set LOW.
After extraction, the ancillary data may be deleted from the video stream by setting the
ANC_DATA_DEL bit of the host interface HIGH. When set HIGH, all existing ancillary
data is removed and replaced with blanking values. If any of the ANC_TYPE registers are
programmed with a DID and/or DID and SDID, only the ancillary data packets with the
matching IDs are deleted from the video stream.
NOTE1: After the ancillary data determined by the ANC_TYPE_X_APX registers has
been deleted, other existing ancillary data may not be contiguous. The device does not
concatenate the remaining ancillary data.
NOTE2: Reading extracted ancillary data from the host interface must be performed
while there is a valid video signal present at the serial input and the device is locked
(LOCKED signal is HIGH).
4.18.9 Level B to Level A Conversion
When IOPROC_2 register bit LEVEL_B2A_CONV_DISABLE_MASK is HIGH (default),
the GS2961 does not convert 3G LEVEL B streams between Level A and Level B mapping
formats.
When LEVEL_B2A_CONV_DISABLE_MASK is LOW, the GS2961 converts a 3G 1080p
Level B stream to the Level A mapping format, as per SMPTE 425M.
The device assumes that Link A and Link B are phase-aligned at the transmitter.
The output data are line multiplexed such that the data content from Link A and Link B
are assembled in a continuous fashion, at twice the input data rate. Extracted timing
reference information is used to trigger a line counter which embeds the correct line
number according to SMPTE 425M.
NOTE 1: If Level B/A conversion is enabled, previous 352M Payload ID packets are not
deleted from the data stream.
NOTE 2: When Level B/A conversion is enabled, timing reference information (FVH)
present on the STAT outputs is not phase-aligned with the output video data, and should
not be used for line or frame synchronization activities. During Level B to Level A
conversion, it is advised that the user generates the H and V timing signals from the
embedded TRS words.
NOTE 3: If the GS2961 sees a synchronous switch where the difference in phases
between two Level B inputs is greater than ~10.7μs, the user may observe a missing H
pulse on the line following the switch line, when Level B/A conversion is enabled.
4.19 GSPI - HOST Interface
The GSPI, or Gennum Serial Peripheral Interface, is a 4-wire interface provided to allow
the system to access additional status and control information through configuration
registers in the GS2961.
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
77 of 104