GS2961 Datasheet, PDF (6/104 Pages) Gennum Corporation – 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing

7.3 Marking Diagram ......................................................................................................................... 102
7.4 Solder Reflow Profiles ................................................................................................................ 103
7.5 Ordering Information ................................................................................................................. 103
List of Figures
Figure 3-1: Digital Input Pin with Schmitt Trigger............................................................................... 23
Figure 3-2: Bidirectional Digital Input/Output Pin.............................................................................. 23
Figure 3-3: Bidirectional Digital Input/Output Pin with programmable drive strength......... 24
Figure 3-4: XTAL1/XTAL2/XTAL-OUT ................................................................................................... 24
Figure 3-5: VBG .............................................................................................................................................. 25
Figure 3-6: LB_CONT .................................................................................................................................... 25
Figure 3-7: Loop Filter .................................................................................................................................. 25
Figure 3-8: SDO/SDO .................................................................................................................................... 26
Figure 3-9: Equalizer Input Equivalent Circuit .................................................................................... 26
Figure 4-1: Level A Mapping ...................................................................................................................... 28
Figure 4-2: Level B Mapping ...................................................................................................................... 28
Figure 4-3: GS2961 Integrated EQ Block Diagram ............................................................................. 30
Figure 4-4: 27MHz Clock Sources ............................................................................................................ 32
Figure 4-5: PCLK to Data and Control Signal Output Timing - SDR Mode 1 .............................. 35
Figure 4-6: PCLK to Data and Control Signal Output Timing - SDR Mode 2 .............................. 36
Figure 4-7: PCLK to Data and Control Signal Output Timing - DDR Mode ................................. 37
Figure 4-8: DDR Video Interface .............................................................................................................. 40
Figure 4-9: Delay Adjustment Ranges .................................................................................................... 41
Figure 4-10: Switch Line Locking on a Non-Standard Switch Line ............................................... 43
Figure 4-11: H:V:F Output Timing - 3G Level A and HDTV 20-bit Mode .................................... 47
Figure 4-12: H:V:F Output Timing - 3G Level A and HDTV 10-bit Mode
3G Level B 20-bit Mode, each 10-bit stream ......................................................................................... 47
Figure 4-13: H:V:F Output Timing - 3G Level B 10-bit Mode .......................................................... 48
Figure 4-14: H:V:F Output Timing - HD 20-bit Output Mode ......................................................... 48
Figure 4-15: H:V:F Output Timing - HD 10-bit Output Mode ......................................................... 48
Figure 4-16: H:V:F Output Timing - SD 20-bit Output Mode .......................................................... 48
Figure 4-17: H:V:F Output Timing - SD 10-bit Output Mode .......................................................... 48
Figure 4-18: H:V:DE Output Timing 1280 x 720p @ 59.94/60 (Format 4) ................................... 50
Figure 4-19: H:V:DE Output Timing 1920 x 1080i @ 59.94/60 (Format 5) ................................. 51
Figure 4-20: H:V:DE Output Timing 720 (1440) x 480i @ 59.94/60 (Format 6&7) .................... 52
Figure 4-21: H:V:DE Output Timing 1280 x 720p @ 50 (Format 19) ............................................. 52
Figure 4-22: H:V:DE Output Timing 1920 x 1080i @ 50 (Format 20) ........................................... 53
Figure 4-23: H:V:DE Output Timing 720 (1440) x 576 @ 50 (Format 21 & 22) ........................... 54
Figure 4-24: H:V:DE Output Timing 1920 x 1080p @ 59.94/60 (Format 16) .............................. 54
Figure 4-25: H:V:DE Output Timing 1920 x 1080p @ 50 (Format 31) .......................................... 55
Figure 4-26: H:V:DE Output Timing 1920 x 1080p @ 23.94/24 (Format 32) .............................. 55
Figure 4-27: H:V:DE Output Timing 1920 x 1080p @ 25 (Format 33) .......................................... 56
Figure 4-28: H:V:DE Output Timing 1920 x 1080p @ 29.97/30 (Format 34) .............................. 56
Figure 4-29: Y/1ANC and C/2ANC Signal Timing .............................................................................. 66
Figure 4-30: Ancillary Data Extraction - Step A .................................................................................. 73
Figure 4-31: Ancillary Data Extraction - Step B ................................................................................... 74
Figure 4-32: Ancillary Data Extraction - Step C .................................................................................. 75
Figure 4-33: Ancillary Data Extraction - Step D .................................................................................. 76
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
6 of 104