GS2961 Datasheet, PDF (63/104 Pages) Gennum Corporation – 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing

Table 4-13: Error Status Register and Error Mask Register
Video Error Status Register
FF_CRC_ERR (02h)
VD_STD_ERR (02h, 03h)
Video Error Mask Register
FF_CRC_ERR_MASK (037h)
VD_STD_ERR_MASK (037h)
NOTE: In 3G Level B mode, separate Video Error Mask registers exist for Link A and Link
B. The GS2961 distinguishes between Level A and Level B mappings at 3Gb/s. When
Level B data is detected, error detection is enabled separately for Data Stream 1 and Data
Stream 2 (Link A and Link B, respectively). Therefore, a second set of error status and
mask registers is available for Data Stream 2, and is only valid when 3Gb/s Level B data
is detected by the device.
4.16.1 TRS Error Detection
TRS error flags are generated by the GS2961 under the following two conditions:
1. A phase shift in received TRS timing is observed on a non-switching line.
2. The received TRS Hamming codes are incorrect.
Both SAV and EAV TRS words are checked for timing and data integrity errors.
For HD mode, only the Y channel TRS codes are checked for errors.
For 3G mode Level A signals, only data stream one TRS codes are checked for errors. For
3G Level B signals, the Y channel TRS codes of both Link A and Link B are checked for
errors.
Both 8-bit and 10-bit TRS code words are checked for errors.
The SAV_ERR bit of the ERROR_STAT_X register is set HIGH when an SAV TRS error is
detected.
The EAV_ERR bit of the ERROR_STAT_X register is set HIGH when an EAV TRS error is
detected.
4.16.2 Line Based CRC Error Detection
The GS2961 calculates line based CRCs for HD and 3G video signals. CRC calculations
are done for each 10-bit channel (Y and C for HD video, DS1 and DS2 for 3G video).
These calculated CRC values are compared with the received CRC values.
If a mismatch in the calculated and received CRC values is detected for Y channel data
(Data Stream 1 for 3G video), the YCRC_ERR bit in the ERROR_STAT_X register is set
HIGH.
If a mismatch in the calculated and received CRC values is detected for C channel data
(Data Stream 2 for 3G video), the CCRC_ERR bit in the ERROR_STAT_X register is set
HIGH.
Y or C CRC errors are also generated if CRC values are not embedded.
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
63 of 104